2009 |
38 | EE | Samantika Subramaniam,
Anne Bracy,
Hong Wang,
Gabriel H. Loh:
Criticality-based optimizations for efficient load processing.
HPCA 2009: 419-430 |
2008 |
37 | EE | Gabriel H. Loh:
A modular 3d processor for flexible product design and technology migration.
Conf. Computing Frontiers 2008: 159-170 |
36 | EE | Samantika Subramaniam,
Milos Prvulovic,
Gabriel H. Loh:
PEEP: Exploiting predictability of memory dependences in SMT processors.
HPCA 2008: 137-148 |
35 | EE | Gabriel H. Loh:
3D-Stacked Memory Architectures for Multi-core Processors.
ISCA 2008: 453-464 |
34 | EE | Gabriel H. Loh,
Daniel A. Jiménez:
Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors.
International Journal of Parallel Programming 36(2): 267-286 (2008) |
2007 |
33 | EE | Kiran Puttaswamy,
Gabriel H. Loh:
Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors.
DAC 2007: 622-625 |
32 | EE | Kiran Puttaswamy,
Gabriel H. Loh:
Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors.
HPCA 2007: 193-204 |
31 | EE | Peter G. Sassone,
Jeff Rupley,
Edward Brekelbaum,
Gabriel H. Loh,
Bryan Black:
Matrix scheduler reloaded.
ISCA 2007: 335-346 |
30 | EE | Peter G. Sassone,
D. Scott Wills,
Gabriel H. Loh:
Static strands: Safely exposing dependence chains for increasing embedded power efficiency.
ACM Trans. Embedded Comput. Syst. 6(4): (2007) |
29 | EE | Gabriel H. Loh,
Yuan Xie,
Bryan Black:
Processor Design in 3D Die-Stacking Technologies.
IEEE Micro 27(3): 31-48 (2007) |
28 | EE | Michael B. Healy,
Mario Vittes,
Mongkol Ekpanyapong,
Chinnakrishnan S. Ballapuram,
Sung Kyu Lim,
Hsien-Hsin S. Lee,
Gabriel H. Loh:
Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 38-52 (2007) |
2006 |
27 | EE | Kiran Puttaswamy,
Gabriel H. Loh:
Dynamic instruction schedulers in a 3-dimensional integration technology.
ACM Great Lakes Symposium on VLSI 2006: 153-158 |
26 | EE | Kiran Puttaswamy,
Gabriel H. Loh:
Thermal analysis of a 3D die-stacked high-performance microprocessor.
ACM Great Lakes Symposium on VLSI 2006: 19-24 |
25 | EE | Chinnakrishnan S. Ballapuram,
Kiran Puttaswamy,
Gabriel H. Loh,
Hsien-Hsin S. Lee:
Entropy-based low power data TLB design.
CASES 2006: 304-311 |
24 | EE | Michael B. Healy,
Mario Vittes,
Mongkol Ekpanyapong,
Chinnakrishnan S. Ballapuram,
Sung Kyu Lim,
Hsien-Hsin S. Lee,
Gabriel H. Loh:
Microarchitectural floorplanning under performance and thermal tradeoff.
DATE 2006: 1288-1293 |
23 | EE | Samantika Subramaniam,
Gabriel H. Loh:
Store vectors for scalable memory dependence prediction and scheduling.
HPCA 2006: 65-76 |
22 | EE | Kiran Puttaswamy,
Gabriel H. Loh:
The impact of 3-dimensional integration on the design of arithmetic units.
ISCAS 2006 |
21 | EE | Gabriel H. Loh:
Revisiting the performance impact of branch predictor latencies.
ISPASS 2006: 59-69 |
20 | EE | Kiran Puttaswamy,
Gabriel H. Loh:
Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology.
ISVLSI 2006: 384-392 |
19 | EE | Samantika Subramaniam,
Gabriel H. Loh:
Fire-and-Forget: Load/Store Scheduling with No Store Queue at All.
MICRO 2006: 273-284 |
18 | EE | Ranjith Subramanian,
Yannis Smaragdakis,
Gabriel H. Loh:
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads.
MICRO 2006: 385-396 |
17 | EE | Bryan Black,
Murali Annavaram,
Ned Brekelbaum,
John DeVale,
Lei Jiang,
Gabriel H. Loh,
Don McCaule,
Pat Morrow,
Donald W. Nelson,
Daniel Pantuso,
Paul Reed,
Jeff Rupley,
Sadasivan Shankar,
John Paul Shen,
Clair Webb:
Die Stacking (3D) Microarchitecture.
MICRO 2006: 469-479 |
16 | EE | Daniel A. Jiménez,
Gabriel H. Loh:
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors.
SBAC-PAD 2006: 55-62 |
15 | EE | Yuan Xie,
Gabriel H. Loh,
Bryan Black,
Kerry Bernstein:
Design space exploration for 3D architectures.
JETC 2(2): 65-103 (2006) |
2005 |
14 | EE | Kiran Puttaswamy,
Gabriel H. Loh:
Implementing Caches in a 3D Technology for High Performance Processors.
ICCD 2005: 525-532 |
13 | EE | Gabriel H. Loh:
A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction.
IEEE PACT 2005: 243-254 |
12 | EE | Gabriel H. Loh:
Simulation Differences Between Academia and Industry: A Branch Prediction Case Study.
ISPASS 2005: 21-31 |
11 | EE | Peter G. Sassone,
D. Scott Wills,
Gabriel H. Loh:
Static strands: safely collapsing dependence chains for increasing embedded power efficiency.
LCTES 2005: 127-136 |
2003 |
10 | EE | Gabriel H. Loh,
Dana S. Henry,
Arvind Krishnamurthy:
Exploiting Bias in the Hysteresis Bit of 2-bit Saturating Counters in Branch Predictors.
J. Instruction-Level Parallelism 5: (2003) |
9 | EE | Gabriel H. Loh:
Width-Partitioned Load Value Predictors.
J. Instruction-Level Parallelism 5: (2003) |
2002 |
8 | EE | Gabriel H. Loh,
Dana S. Henry:
Applying Machine Learning for Ensemble Branch Predictors.
IEA/AIE 2002: 264-274 |
7 | EE | Gabriel H. Loh,
Dana S. Henry:
Predicting Conditional Branches With Fusion-Based Hybrid Predictors.
IEEE PACT 2002: 165- |
6 | EE | Dana S. Henry,
Gabriel H. Loh,
Rahul Sami:
Speculative Clustered Caches for Clustered Processors.
ISHPC 2002: 281-290 |
5 | EE | Gabriel H. Loh:
Exploiting data-width locality to increase superscalar execution bandwidth.
MICRO 2002: 395-405 |
4 | EE | Bradley C. Kuszmaul,
Dana S. Henry,
Gabriel H. Loh:
A Comparison of Asymptotically Scalable Superscalar Processors.
Theory Comput. Syst. 35(2): 129-150 (2002) |
2001 |
3 | EE | Gabriel H. Loh:
A time-stamping algorithm for efficient performance estimation of superscalar processors.
SIGMETRICS/Performance 2001: 72-81 |
2000 |
2 | EE | Dana S. Henry,
Bradley C. Kuszmaul,
Gabriel H. Loh,
Rahul Sami:
Circuits for wide-window superscalar processors.
ISCA 2000: 236-247 |
1999 |
1 | EE | Bradley C. Kuszmaul,
Dana S. Henry,
Gabriel H. Loh:
A Comparison of Scalable Superscalar Processors.
SPAA 1999: 126-137 |