Evangeline F. Y. Young

F. Y. Young, Fung Yu Young

2009
51	EE	Chiu-Wing Sham, Evangeline F. Y. Young, Jingwei Lu: Congestion prediction in early stages of physical design. ACM Trans. Design Autom. Electr. Syst. 14(1): (2009)
2008
50	EE	Tilen Ma, Evangeline F. Y. Young: TCG-based multi-bend bus driven floorplanning. ASP-DAC 2008: 192-197
49	EE	Qiang Ma, Evangeline F. Y. Young: Network flow-based power optimization under timing constraints in MSV-driven floorplanning. ICCAD 2008: 1-8
48	EE	Liang Li, Evangeline F. Y. Young: Obstacle-avoiding rectilinear Steiner tree construction. ICCAD 2008: 523-528
47	EE	Renshen Wang, Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng: 3-D floorplanning using labeled tree and dual sequences. ISPD 2008: 54-59
46	EE	Evangeline F. Y. Young: Slicing Floorplan Orientation. Encyclopedia of Algorithms 2008
45	EE	Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou: Optimizing wirelength and routability by searching alternative packings in floorplanning. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008)
44	EE	Jill H. Y. Law, Evangeline F. Y. Young: Multi-bend bus driven floorplanning. Integration 41(2): 306-316 (2008)
2007
43	EE	Qiang Ma, Evangeline F. Y. Young, K. P. Pun: Analog placement with common centroid constraints. ICCAD 2007: 579-585
42	EE	Qiang Ma, Evangeline F. Y. Young: Voltage island-driven floorplanning. ICCAD 2007: 644-649
41	EE	Chiu-Wing Sham, Evangeline F. Y. Young: Area reduction by deadspace utilization on interconnect optimized floorplan. ACM Trans. Design Autom. Electr. Syst. 12(1): (2007)
40	EE	Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu: Wire Retiming Problem With Net Topology Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1648-1660 (2007)
2006
39	EE	Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S. Ching: Block alignment in 3D floorplan using layered TCG. ACM Great Lakes Symposium on VLSI 2006: 376-380
38	EE	Royce L. S. Ching, Evangeline F. Y. Young: Shuttle mask floorplanning with modified alpha-restricted grid. ACM Great Lakes Symposium on VLSI 2006: 85-90
37	EE	Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu: Optimal cell flipping in placement and floorplanning. DAC 2006: 1109-1114
36	EE	Qiang Xu, Baosheng Wang, F. Y. Young: Retention-Aware Test Scheduling for BISTed Embedded SRAMs. European Test Symposium 2006: 83-88
35	EE	Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu: Analog placement with symmetry and other placement constraints. ICCAD 2006: 349-354
34	EE	Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu: Post-placement voltage island generation. ICCAD 2006: 641-646
2005
33	EE	Chiu-Wing Sham, Evangeline F. Y. Young: Congestion prediction in floorplanning. ASP-DAC 2005: 1107-1110
32	EE	Jill H. Y. Law, Evangeline F. Y. Young: Multi-bend bus driven floorplanning. ISPD 2005: 113-120
31	EE	Chiu-Wing Sham, Evangeline F. Y. Young: Congestion prediction in early stages. SLIP 2005: 91-98
2004
30	EE	Dennis K. Y. Tong, Evangeline F. Y. Young: Performance-driven register insertion in placement. ISPD 2004: 53-60
29	EE	Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho: Placement constraints in floorplan design. IEEE Trans. VLSI Syst. 12(7): 735-745 (2004)
28	EE	Chris C. N. Chu, Evangeline F. Y. Young: Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 71-79 (2004)
2003
27	EE	Eric S. H. Wong, Evangeline F. Y. Young, Wai-Kei Mak: Clustering based acyclic multi-way partitioning. ACM Great Lakes Symposium on VLSI 2003: 203-206
26	EE	Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu: A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. DATE 2003: 10856-10861
25	EE	Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu: Retiming with Interconnect and Gate Delay. ICCAD 2003: 221-226
24	EE	Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen: Twin binary sequences: a nonredundant representation for general nonslicing floorplan. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 457-469 (2003)
23	EE	Chiu-Wing Sham, Evangeline F. Y. Young: Routability-driven floorplanner with buffer block planning. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 470-480 (2003)
22	EE	Wing Seung Yuen, Evangeline F. Y. Young: Slicing floorplan with clustering constraint. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 652-658 (2003)
21	EE	Wai-Kei Mak, Evangeline F. Y. Young: Temporal logic replication for dynamically reconfigurable FPGA partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 952-959 (2003)
2002
20	EE	Chris C. N. Chu, Evangeline F. Y. Young: Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. DATE 2002: 1101
19	EE	Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Young: Congestion Estimation with Buffer Planning in Floorplan Design. DATE 2002: 696-701
18	EE	Wai-Kei Mak, Evangeline F. Y. Young: Temporal logic replication for dynamically reconfigurable FPGA partitioning. ISPD 2002: 190-195
17	EE	Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen: Twin binary sequences: a non-redundant representation for general non-slicing floorplan. ISPD 2002: 196-201
16	EE	Chiu-Wing Sham, Evangeline F. Y. Young: Routability driven floorplanner with buffer block planning. ISPD 2002: 50-55
15	EE	Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho: A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. VLSI Design 2002: 661-
2001
14	EE	Wing Seung Yuen, Fung Yu Young: Slicing floorplan with clustering constraints. ASP-DAC 2001: 503-508
13	EE	Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong: Handling soft modules in general nonslicing floorplan usingLagrangian relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 687-692 (2001)
12	EE	Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang: On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 800-807 (2001)
2000
11	EE	Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong: Floorplan area minimization using Lagrangian relaxation. ISPD 2000: 174-179
10	EE	Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang: Slicing floorplans with range constraint. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 272-278 (2000)
1999
9	EE	Fung Yu Young, D. F. Wong: Slicing Floorplans with Boundary Constraint. ASP-DAC 1999: 17-20
8	EE	Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani: Integrated floorplanning and interconnect planning. ICCAD 1999: 354-357
7	EE	Fung Yu Young, D. F. Wong: Slicing floorplans with range constraint. ISPD 1999: 97-102
6	EE	Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang: Slicing floorplans with boundary constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1385-1389 (1999)
5	EE	Fung Yu Young, Chris C. N. Chu, D. F. Wong: Generation of Universal Series-Parallel Boolean Functions. J. ACM 46(3): 416-435 (1999)
1998
4	EE	Fung Yu Young, D. F. Wong: Slicing floorplans with pre-placed modules. ICCAD 1998: 252-258
1997
3		Fung Yu Young, D. F. Wong: On the Construction of Universal Series-Parallel Functions for Logic Module Design. ICCD 1997: 482-488
2	EE	Fung Yu Young, D. F. Wong: How good are slicing floorplans?. ISPD 1997: 144-149
1	EE	F. Y. Young, D. F. Wong: How good are slicing floorplans? Integration 23(1): 61-73 (1997)

Coauthor Index

1	Hung-Ming Chen	[8]
2	Chung-Kuan Cheng	[47]
3	Royce L. S. Ching	[34] [38] [39]
4	Chris C. N. Chu (Chris Chong-Nuen Chu)	[5] [11] [13] [15] [17] [20] [24] [25] [26] [28] [29] [34] [35] [37] [40]
5	Fan R. K. Chung (Fan Chung Graham)	[47]
6	Sampath Dechu	[25] [40]
7	Ronald L. Graham	[47]
8	M. L. Ho	[15] [29]
9	Steve T. W. Lai	[26]
10	Jill H. Y. Law	[32] [39] [44]
11	Kevin C. K. Leung	[34]
12	Liang Li	[48]
13	Jingwei Lu	[51]
14	W. S. Luk	[11] [13]
15	Qiang Ma (Ma Qiang)	[42] [43] [49]
16	Tilen Ma	[50]
17	Wai-Kei Mak	[18] [21] [27]
18	K. P. Pun	[43]
19	Chiu-Wing Sham	[16] [19] [23] [31] [33] [37] [41] [45] [51]
20	Zion Cien Shen	[17] [24]
21	Naveed A. Sherwani	[8]
22	Yiu-Cheong Tam	[35]
23	Dennis K. Y. Tong	[25] [30] [40]
24	Baosheng Wang	[36]
25	Renshen Wang	[47]
26	Eric S. H. Wong	[27]
27	Martin D. F. Wong (D. F. Wong)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [12]
28	Wai-Chiu Wong	[19]
29	Y. C. Wong	[11] [13]
30	Qiang Xu	[36]
31	Hannah Honghua Yang (Honghua Yang)	[6] [8] [10] [12]
32	Wing Seung Yuen	[14] [22]
33	Hai Zhou	[8] [45]
34	Yi Zhu	[47]

Colors in the list of coauthors