| 2007 |
|---|
| 8 | EE | Shuo Zhou,
Bo Yao,
Hongyu Chen,
Yi Zhu,
Michael Hutton,
Truman Collins,
Sridhar Srinivasan,
Nan-Chi Chou,
Peter Suaris,
Chung-Kuan Cheng:
Efficient Timing Analysis With Known False Paths Using Biclique Covering.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 959-969 (2007) |
| 2006 |
|---|
| 7 | EE | Shuo Zhou,
Bo Yao,
Hongyu Chen,
Yi Zhu,
Chung-Kuan Cheng,
Michael Hutton:
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths.
ASP-DAC 2006: 73-78 |
| 6 | EE | Shuo Zhou,
Yi Zhu,
Yuanfang Hu,
Ronald L. Graham,
Mike Hutton,
Chung-Kuan Cheng:
Timing model reduction for hierarchical timing analysis.
ICCAD 2006: 415-422 |
| 2005 |
|---|
| 5 | EE | Shuo Zhou,
Bo Yao,
Jianhua Liu,
Chung-Kuan Cheng:
Integrated algorithmic logical and physical design of integer multiplier.
ASP-DAC 2005: 1014-1017 |
| 4 | | Shuo Zhou,
Bo Yao,
Hongyu Chen,
Yi Zhu,
Chung-Kuan Cheng,
Michael Hutton,
Truman Collins,
Sridhar Srinivasan,
Nan-Chi Chou,
Peter Suaris:
Improving the efficiency of static timing analysis with false paths.
ICCAD 2005: 527-531 |
| 2003 |
|---|
| 3 | EE | Jianhua Liu,
Shuo Zhou,
Haikun Zhu,
Chung-Kuan Cheng:
An Algorithmic Approach for Generic Parallel Adders.
ICCAD 2003: 734-740 |
| 2002 |
|---|
| 2 | EE | Sheqin Dong,
Shuo Zhou,
Xianlong Hong,
Chung-Kuan Cheng,
Jun Gu,
Yici Cai:
An Optimum Placement Search Algorithm Based on Extended Corner Block List.
J. Comput. Sci. Technol. 17(6): 699-707 (2002) |
| 2001 |
|---|
| 1 | EE | Shuo Zhou,
Sheqin Dong,
Chung-Kuan Cheng,
Jun Gu:
ECBL: an extended corner block list with solution space including optimum placement.
ISPD 2001: 150-155 |
