2008 |
17 | EE | Ashish Srivastava,
Kaviraj Chopra,
Saumil Shah,
Dennis Sylvester,
David Blaauw:
A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 272-285 (2008) |
16 | EE | David Blaauw,
Kaviraj Chopra,
Ashish Srivastava,
Louis Scheffer:
Statistical Timing Analysis: From Basic Principles to State of the Art.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 589-607 (2008) |
2007 |
15 | EE | Ashish Srivastava,
T. Kachru,
Dennis Sylvester:
Low-Power-Design Space Exploration Considering Process Variation Using Robust Optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 67-79 (2007) |
2005 |
14 | EE | Ashish Srivastava,
Saumil Shah,
Kanak Agarwal,
Dennis Sylvester,
David Blaauw,
Stephen W. Director:
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance.
DAC 2005: 535-540 |
13 | | Kaviraj Chopra,
Saumil Shah,
Ashish Srivastava,
David Blaauw,
Dennis Sylvester:
Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation.
ICCAD 2005: 1023-1028 |
12 | | Saumil Shah,
Ashish Srivastava,
Dushyant Sharma,
Dennis Sylvester,
David Blaauw,
Vladimir Zolotov:
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation.
ICCAD 2005: 705-712 |
2004 |
11 | EE | Ashish Srivastava,
Dennis Sylvester,
David Blaauw:
Statistical optimization of leakage power considering process variations using dual-Vth and sizing.
DAC 2004: 773-778 |
10 | EE | Ashish Srivastava,
Dennis Sylvester,
David Blaauw:
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment.
DAC 2004: 783-787 |
9 | EE | Ashish Srivastava,
Dennis Sylvester,
David Blaauw:
Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design.
DATE 2004: 718-719 |
8 | EE | Ashish Srivastava,
Dennis Sylvester:
A general framework for probabilistic low-power design space exploration considering process variation.
ICCAD 2004: 808-813 |
7 | EE | Sarvesh H. Kulkarni,
Ashish Srivastava,
Dennis Sylvester:
A new algorithm for improved VDD assignment in low power dual VDD systems.
ISLPED 2004: 200-205 |
6 | | Rajeev R. Rao,
Ashish Srivastava,
David Blaauw,
Dennis Sylvester:
Statistical analysis of subthreshold leakage current for VLSI circuits.
IEEE Trans. VLSI Syst. 12(2): 131-139 (2004) |
5 | EE | Ashish Srivastava,
Dennis Sylvester:
Minimizing total power by simultaneous V/sub dd//V/sub th/ assignment.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 665-677 (2004) |
2003 |
4 | EE | Ruchir Puri,
Leon Stok,
John M. Cohn,
David S. Kung,
David Z. Pan,
Dennis Sylvester,
Ashish Srivastava,
Sarvesh H. Kulkarni:
Pushing ASIC performance in a power envelope.
DAC 2003: 788-793 |
3 | EE | Rajeev R. Rao,
Ashish Srivastava,
David Blaauw,
Dennis Sylvester:
Statistical estimation of leakage current considering inter- and intra-die process variation.
ISLPED 2003: 84-89 |
2 | EE | Robert Bai,
Sarvesh H. Kulkarni,
Wesley Kwong,
Ashish Srivastava,
Dennis Sylvester,
David Blaauw:
An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages.
ISVLSI 2003: 149-154 |
2002 |
1 | EE | Ashish Srivastava,
Robert Bai,
David Blaauw,
Dennis Sylvester:
Modeling and analysis of leakage power considering within-die process variations.
ISLPED 2002: 64-67 |