| 2009 |
|---|
| 9 | EE | Andrew C. Ling,
Stephen Dean Brown,
Jianwen Zhu,
Sean Safarpour:
Towards automated ECOs in FPGAs.
FPGA 2009: 3-12 |
| 2008 |
|---|
| 8 | EE | Andrew C. Ling,
Jianwen Zhu,
Stephen Dean Brown:
Delay driven AIG restructuring using slack budget management.
ACM Great Lakes Symposium on VLSI 2008: 163-166 |
| 7 | EE | Andrew C. Ling,
Jianwen Zhu,
Stephen Dean Brown:
Scalable Synthesis and Clustering Techniques Using Decision Diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 423-435 (2008) |
| 2007 |
|---|
| 6 | EE | Andrew C. Ling,
Jianwen Zhu,
Stephen Dean Brown:
BddCut: Towards Scalable Symbolic Cut Enumeration.
ASP-DAC 2007: 408-413 |
| 5 | EE | Andrew C. Ling,
Deshanand P. Singh,
Stephen Dean Brown:
Incremental placement for structured ASICs using the transportation problem.
VLSI-SoC 2007: 172-177 |
| 4 | EE | Andrew C. Ling,
Deshanand P. Singh,
Stephen Dean Brown:
FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1196-1210 (2007) |
| 2005 |
|---|
| 3 | EE | Andrew C. Ling,
Deshanand P. Singh,
Stephen Dean Brown:
FPGA technology mapping: a study of optimality.
DAC 2005: 427-432 |
| 2 | | Andrew C. Ling,
Deshanand P. Singh,
Stephen Dean Brown:
FPGA PLB Evaluation using Quantified Boolean Satisfiability.
FPL 2005: 19-24 |
| 1 | EE | Andrew C. Ling,
Deshanand P. Singh,
Stephen Dean Brown:
FPGA Logic Synthesis Using Quantified Boolean Satisfiability.
SAT 2005: 444-450 |
