2008 | ||
---|---|---|
77 | EE | Sung-Boem Park, Subhasish Mitra: IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors. DAC 2008: 373-378 |
76 | EE | Jie Zhang, Nishant Patil, Subhasish Mitra: Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits. DATE 2008: 1009-1014 |
75 | EE | Neeraj Suri, Christof Fetzer, Jacob Abraham, Stefan Poledna, Avi Mendelson, Subhasish Mitra: Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems. DATE 2008: 1394-1395 |
74 | EE | Yanjing Li, Samy Makar, Subhasish Mitra: CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns. DATE 2008: 885-890 |
73 | EE | Subhasish Mitra: Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges. DATE 2008: 941-946 |
72 | EE | Dimitris Gizopoulos, Kaushik Roy, Subhasish Mitra, Pia Sanda: Soft Errors: System Effects, Protection Techniques and Case Studies. DATE 2008 |
71 | EE | Subhasish Mitra, Ravishankar K. Iyer, Kishor S. Trivedi, James W. Tschanz: Reliable system design: models, metrics and design techniques. ICCAD 2008: 3 |
70 | EE | Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini: A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. ICCAD 2008: 598-602 |
69 | EE | Subhasish Mitra: Tutorial 4: Robust System Design in Scaled CMOS. ISQED 2008: 6 |
68 | EE | Tze Wee Chen, Kyunglok Kim, Young Moon Kim, Subhasish Mitra: Gate-Oxide Early Life Failure Prediction. VTS 2008: 111-118 |
67 | EE | Rohit Kapur, Subhasish Mitra, Thomas W. Williams: Historical Perspective on Scan Compression. IEEE Design & Test of Computers 25(2): 114-120 (2008) |
66 | EE | Nishant Patil, Jie Deng, Albert Lin, H.-S. Philip Wong, Subhasish Mitra: Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1725-1736 (2008) |
2007 | ||
65 | EE | Nishant Patil, Jie Deng, H.-S. Philip Wong, Subhasish Mitra: Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits. DAC 2007: 958-961 |
64 | EE | Sanjit A. Seshia, Wenchao Li, Subhasish Mitra: Verification-guided soft error resilience. DATE 2007: 1442-1447 |
63 | EE | Subhasish Mitra: Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout. IOLTS 2007: 123 |
62 | EE | Subhasish Mitra, Pia Sanda, Norbert Seifert: Soft Errors: Technology Trends, System Effects, and Protection Techniques. IOLTS 2007: 4 |
61 | EE | Mridul Agarwal, Bipul C. Paul, Ming Zhang, Subhasish Mitra: Circuit Failure Prediction and Its Application to Transistor Aging. VTS 2007: 277-286 |
60 | EE | Mehdi Baradaran Tahoori, Subhasish Mitra: Application-Dependent Delay Testing of FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 553-563 (2007) |
2006 | ||
59 | EE | T. M. Mak, Subhasish Mitra: Should Logic SER be Solved at the Circuit Level? IOLTS 2006: 199 |
58 | EE | Bob Mungamuru, Hector Garcia-Molina, Subhasish Mitra: How To Safeguard Your Sensitive Data. SRDS 2006: 199-211 |
57 | EE | Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim: Soft Error Resilient System Design through Error Correction. VLSI-SoC 2006: 332-337 |
56 | EE | Ruifeng Guo, Subhasish Mitra, Enamul Amyeen, Jinkyu Lee, Srihari Sivaraj, Srikanth Venkataraman: Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive. VTS 2006: 66-71 |
55 | EE | Subhasish Mitra, Kee Sup Kim: XPAND: An Efficient Test Stimulus Compression Technique. IEEE Trans. Computers 55(2): 163-173 (2006) |
54 | EE | Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, N. J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, S. J. Patel: Sequential Element Design With Built-In Soft Error Resilience. IEEE Trans. VLSI Syst. 14(12): 1368-1378 (2006) |
2005 | ||
53 | EE | Erik H. Volkerink, Subhasish Mitra: Response compaction with any number of unknowns using a new LFSR architecture. DAC 2005: 117-122 |
52 | EE | Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang: Logic soft errors in sub-65nm technologies design and CAD challenges. DAC 2005: 2-4 |
51 | EE | T. M. Mak, Subhasish Mitra, Ming Zhang: DFT Assisted Built-In Soft Error Resilience. IOLTS 2005: 69 |
50 | EE | R. D. (Shawn) Blanton, Subhasish Mitra: Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead. VLSI Design 2005: 8-9 |
49 | EE | Subhasish Mitra, Norbert Seifert, Ming Zhang, Quan Shi, Kee Sup Kim: Subhasish Mitra, Norbert Seifert, Ming Zhang, Quan Shi, Kee Sup Kim. IEEE Computer 38(2): 43-52 (2005) |
48 | EE | Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher, Nishant Patil: X-Tolerant Test Response Compaction. IEEE Design & Test of Computers 22(6): 566-574 (2005) |
47 | EE | Ravishankar K. Iyer, Nithin Nakka, Zbigniew Kalbarczyk, Subhasish Mitra: Recent Advances and New Avenues in Hardware-Level Reliability Support. IEEE Micro 25(6): 18-29 (2005) |
46 | EE | Mehdi Baradaran Tahoori, Subhasish Mitra: Application-independent testing of FPGA interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1774-1783 (2005) |
45 | EE | Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey: Optimized reseeding by seed ordering and encoding. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 264-270 (2005) |
2004 | ||
44 | EE | Mehdi Baradaran Tahoori, Subhasish Mitra: Defect and Fault Tolerance of Reconfigurable Molecular Computing. FCCM 2004: 176-185 |
43 | EE | Kenneth A. Brand, Erik H. Volkerink, Edward J. McCluskey, Subhasish Mitra: Speed Clustering of Integrated Circuits. ITC 2004: 1128-1137 |
42 | EE | Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher: X-Tolerant Signature Analysis. ITC 2004: 432-441 |
41 | EE | Mehdi Baradaran Tahoori, Subhasish Mitra: Interconnect Delay Testing of Designs on Programmable Logic Devices. ITC 2004: 635-644 |
40 | EE | Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, François-Fabien Ferhani, Edward Li, Subhasish Mitra: ELF-Murphy Data on Defects and Test Sets. VTS 2004: 16-22 |
39 | EE | Subhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger: Delay Defect Screening using Process Monitor Structures. VTS 2004: 43-52 |
38 | EE | Subhasish Mitra, Wei-Je Huang, Nirmal R. Saxena, Shu-Yi Yu, Edward J. McCluskey: Reconfigurable Architecture for Autonomous Self-Repair. IEEE Design & Test of Computers 21(3): 228-240 (2004) |
37 | EE | Vladimir Hahanov, Raimund Ubar, Subhasish Mitra: Conference Reports. IEEE Design & Test of Computers 21(6): 594-595 (2004) |
36 | EE | Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey: Efficient Design Diversity Estimation for Combinational Circuits. IEEE Trans. Computers 53(11): 1483-1492 (2004) |
35 | EE | Mehdi Baradaran Tahoori, Subhasish Mitra: Techniques and algorithms for fault grading of FPGA interconnect test configurations. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 261-272 (2004) |
34 | EE | Subhasish Mitra, Kee Sup Kim: X-compact: an efficient response compaction technique. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 421-432 (2004) |
2003 | ||
33 | EE | Subhasish Mitra, Kee Sup Kim: XMAX: X-Tolerant Architecture for MAXimal Test Compression. ICCD 2003: 326-330 |
32 | EE | David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Kim, Anil Sabbavarapu, Talal Jaber, Pete Johnson, Dale March, Greg Parrish: H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing. ITC 2003: 1229-1238 |
31 | EE | Mehdi Baradaran Tahoori, Subhasish Mitra: Automatic Configuration Generation for FPGA Interconnect Testing. VTS 2003: 134-144 |
30 | EE | Erik H. Volkerink, Subhasish Mitra: Efficient Seed Utilization for Reseeding based Compression. VTS 2003: 232-240 |
29 | EE | Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey: Bist Reseeding with very few Seeds. VTS 2003: 69-76 |
28 | EE | Kee Sup Kim, Subhasish Mitra, Paul G. Ryan: Delay Defect Characteristics and Testing Strategies. IEEE Design & Test of Computers 20(5): 8-16 (2003) |
2002 | ||
27 | EE | Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey: Testing Digital Circuits with Constraints. DFT 2002: 195-206 |
26 | EE | Subhasish Mitra, Edward J. McCluskey: Dependable Reconfigurable Computing Design Diversity and Self Repair. Evolvable Hardware 2002: 5 |
25 | EE | Erik H. Volkerink, Ajay Khoche, Subhasish Mitra: Packet-Based Input Test Data Compression Techniques. ITC 2002: 154-163 |
24 | EE | Subhasish Mitra, Kee Sup Kim: X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction. ITC 2002: 311-320 |
23 | EE | Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin Toutounchi, Edward J. McCluskey: Fault Grading FPGA Interconnect Test Configurations. ITC 2002: 608-617 |
22 | EE | Subhasish Mitra, Edward J. McCluskey, Samy Makar: Design for Testability and Testing of IEEE 1149.1 Tap Controller. VTS 2002: 247-252 |
21 | EE | Edward J. McCluskey, Subhasish Mitra, Bob Madge, Peter C. Maxwell, Phil Nigh, Mike Rodgers: Debating the Future of Burn-In. VTS 2002: 311-314 |
20 | EE | Ajay Khoche, Erik H. Volkerink, Jochen Rivoir, Subhasish Mitra: Test Vector Compression Using EDA-ATE Synergies. VTS 2002: 97-102 |
19 | EE | Nahmsuk Oh, Subhasish Mitra, Edward J. McCluskey: ED4I: Error Detection by Diverse Data and Duplicated Instructions. IEEE Trans. Computers 51(2): 180-199 (2002) |
18 | EE | Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey: A Design Diversity Metric and Analysis of Redundant Systems. IEEE Trans. Computers 51(5): 498-510 (2002) |
2001 | ||
17 | EE | Wei-Je Huang, Subhasish Mitra, Edward J. McCluskey: Fast Run-Time Fault Location in Dependable FPGA-Based Applications. DFT 2001: 206-214 |
16 | EE | Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey: Techniques for Estimation of Design Diversity for Combinational Logic Circuits. DSN 2001: 25-36 |
15 | EE | Subhasish Mitra, Edward J. McCluskey: Diversity Techniques for Concurrent Error Detection. ISQED 2001: 249-250 |
14 | EE | Subhasish Mitra, Edward J. McCluskey: Design Diversity for Concurrent Error Detection in Sequential Logic Circuts. VTS 2001: 178-183 |
13 | EE | Subhasish Mitra, Edward J. McCluskey: Design of Redundant Systems Protected Against Common-Mode Failures. VTS 2001: 190-197 |
12 | EE | Chao-Wen Tseng, Subhasish Mitra, Edward J. McCluskey, Scott Davidson: An Evaluation of Pseudo Random Testing for Detecting Real Defects. VTS 2001: 404-410 |
2000 | ||
11 | EE | Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken: DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits. ASYNC 2000: 73- |
10 | Subhasish Mitra, Edward J. McCluskey: Combinational logic synthesis for diversity in duplex systems. ITC 2000: 179-188 | |
9 | Subhasish Mitra, Edward J. McCluskey: Which concurrent error detection scheme to choose ? ITC 2000: 985-994 | |
8 | EE | Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey: Fault Escapes in Duplex Systems. VTS 2000: 453-458 |
7 | EE | Subhasish Mitra, Edward J. McCluskey: Word Voter: A New Voter Design for Triple Modular Redundant Systems. VTS 2000: 465-470 |
6 | EE | Nirmal R. Saxena, Santiago Fernández-Gomez, Wei-Je Huang, Subhasish Mitra, Shu-Yi Yu, Edward J. McCluskey: Dependable Computing and Online Testing in Adaptive and Configurable Systems. IEEE Design & Test of Computers 17(1): 29-41 (2000) |
5 | EE | Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey: Efficient Multiplexer Synthesis Techniques. IEEE Design & Test of Computers 17(4): 90-97 (2000) |
1999 | ||
4 | Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey: A design diversity metric and reliability analysis for redundant systems. ITC 1999: 662-671 | |
3 | EE | Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey: An output encoding problem and a solution technique. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 761-768 (1999) |
1997 | ||
2 | EE | Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey: An output encoding problem and a solution technique. ICCAD 1997: 304-307 |
1 | Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey: Scan Synthesis for One-Hot Signals. ITC 1997: 714-722 |