Felice Balarin

2008
51	EE	Eric Cheung, Harry Hsieh, Felice Balarin: Software optimization for MPSoC: a mpeg-2 decoder case study. CODES+ISSS 2008: 43-48
2007
50	EE	Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin: Assertion-Based Design Exploration of DVS in Network Processor Architectures CoRR abs/0710.4714: (2007)
49	EE	Felice Balarin, Roberto Passerone: Specification, Synthesis, and Simulation of Transactor Processes. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1749-1762 (2007)
2006
48	EE	Felice Balarin, Roberto Passerone: Functional verification methodology based on formal interface specification and transactor generation. DATE 2006: 1013-1018
47	EE	Guang Yang, Xi Chen, Felice Balarin, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli: Communication and co-simulation infrastructure for heterogeneous system integration. DATE 2006: 462-467
46	EE	Xi Chen, Harry Hsieh, Felice Balarin: Verification Approach of Metropolis Design Framework for Embedded Systems. International Journal of Parallel Programming 34(1): 3-27 (2006)
2005
45	EE	Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin: Assertion-Based Design Exploration of DVS in Network Processor Architectures. DATE 2005: 92-97
44	EE	Felice Balarin, Claudio Passerone, Alessandro Pinto, Alberto L. Sangiovanni-Vincentelli: A formal approach to system level design: metamodels and unified design environments. MEMOCODE 2005: 155-163
2004
43	EE	Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin: Utilizing Formal Assertions for System Design of Network Processors. DATE 2004: 126-133
42	EE	Guang Yang, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Felice Balarin: Separation of concerns: overhead in modeling and efficient simulation techniques. EMSOFT 2004: 44-53
41	EE	Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe: Logic of constraints: a quantitative performance and functional constraint formalism. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1243-1255 (2004)
2003
40	EE	Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe: Case Studies of Model Checking for Embedded System Designs. ACSD 2003: 20-28
39	EE	Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe: Automatic trace analysis for logic of constraints. DAC 2003: 460-465
38	EE	Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe: Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. DATE 2003: 11174-11175
37	EE	Felice Balarin, Yosinori Watanabe, Harry Hsieh, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli: Metropolis: An Integrated Electronic System Design Environment. IEEE Computer 36(4): 45-52 (2003)
2002
36	EE	Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Guang Yang: Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model. CODES 2002: 13-18
35	EE	Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Marco Sgroi, Yosinori Watanabe: Modeling and Designing Heterogeneous Systems. Concurrency and Hardware Design 2002: 228-273
34	EE	Felice Balarin, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe: Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis. EMSOFT 2002: 407-416
2001
33	EE	Felice Balarin: STARS of MPEG decoder: a case study in worst-case analysis of discrete-event systems. CODES 2001: 104-108
32	EE	Felice Balarin: Stars in VCC: Complementing Simulation with Worst-Case Analysis. ICCAD 2001: 471-
31	EE	Marco Di Natale, Alberto L. Sangiovanni-Vincentelli, Felice Balarin: Scheduling Reactive Task Graphs in Embedded Control Systems. IEEE Real Time Technology and Applications Symposium 2001: 191-
30	EE	Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli: Synchronous approach to the functional equivalence of embeddedsystem implementations. IEEE Trans. on CAD of Integrated Circuits and Systems 20(8): 1016-1033 (2001)
2000
29	EE	Marco Di Natale, Alberto L. Sangiovanni-Vincentelli, Felice Balarin: Task scheduling with RT constraints. DAC 2000: 483-488
28	EE	Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli: Efficient methods for embedded system design space exploration. DAC 2000: 607-612
27	EE	Felice Balarin: Automatic Abstraction for Worst-Case Analysis of Discrete Systems. DATE 2000: 494-501
26	EE	Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Sequential synthesis using S1S. IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1149-1162 (2000)
1999
25	EE	Felice Balarin: Worst-case analysis of discrete systems based on conditional abstractions. CODES 1999: 115-119
24	EE	Felice Balarin: Worst-case analysis of discrete systems. ICCAD 1999: 347-353
23	EE	Harry Hsieh, Felice Balarin: Synchronous equivalence for embedded systems: a tool for design exploration. ICCAD 1999: 505-510
22	EE	Felice Balarin, Massimiliano Chiodo: Software Synthesis for Complex Reactive Embedded Systems. ICCD 1999: 634-639
21	EE	Felice Balarin: Concurrent Symbolic Verification of Liveness Properties for Interleaved Models. Electr. Notes Theor. Comput. Sci. 23(2): (1999)
20	EE	Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich, Kei Suzuki: Synthesis of software programs for embedded control applications. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 834-849 (1999)
1998
19		Felice Balarin: Correctness of the Concurrent Approach to Symbolic Verification of Interleaved Models. CAV 1998: 391-402
18	EE	Felice Balarin: Priority Assignment for Embedded Reactive Real-Time Systems. LCTES 1998: 146-155
17	EE	Felice Balarin, Luciano Lavagno, Praveen K. Murthy, Alberto L. Sangiovanni-Vincentelli: Scheduling for Embedded Real-Time Systems. IEEE Design & Test of Computers 15(1): 71-82 (1998)
1997
16	EE	Felice Balarin, Massimiliano Chiodo, Attila Jurecska, Luciano Lavagno, Bassam Tabbara, Alberto L. Sangiovanni-Vincentelli: Automatic Generation of a Real-Time Operating System for Embedded Systems. CODES 1997: 95-100
15	EE	Felice Balarin, Alberto L. Sangiovanni-Vincentelli: Schedule Validation for Embedded Reactive Real-Time Systems. DAC 1997: 52-57
14	EE	Felice Balarin: Verifying invariants by approximate image computation. Electr. Notes Theor. Comput. Sci. 9: (1997)
1996
13	EE	Felice Balarin, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli: Formal Verification of Embedded Systems based on CFSM Networks. DAC 1996: 568-571
12	EE	Felice Balarin: Approximate reachability analysis of timed automata. IEEE Real-Time Systems Symposium 1996: 52-61
1995
11		Adnan Aziz, Vigyan Singhal, Felice Balarin: It Usually Works: The Temporal Logic of Stochastic Systems. CAV 1995: 155-165
10		Adnan Aziz, Felice Balarin, Robert K. Brayton, M. D. DiBenedetto, Alexander Saldanha: Supervisory Control of Finite State Machines. CAV 1995: 279-292
9	EE	Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Sequential synthesis using S1S. ICCAD 1995: 612-617
8		Felice Balarin, Alberto L. Sangiovanni-Vincentelli: An Iterative Approach to Verification of Real-Time Systems. Formal Methods in System Design 6(1): 67-95 (1995)
1994
7		Felice Balarin, Alberto L. Sangiovanni-Vincentelli: On the Automatic Computation of Network Invariants. CAV 1994: 234-246
6	EE	Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: HSIS: A BDD-Based Environment for Formal Verification. DAC 1994: 454-459
5		Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Equivalences for Fair Kripke Structures. ICALP 1994: 364-375
4	EE	Felice Balarin, Alberto L. Sangiovanni-Vincentelli: Iterative algorithms for formal verification of embedded real-time systems. ICCAD 1994: 450-457
1993
3		Felice Balarin, Alberto L. Sangiovanni-Vincentelli: An Iterative Approach to Language Containment. CAV 1993: 29-40
2		Felice Balarin, Gary York: Verilog HDL Modeling Styles for Formal Verification. CHDL 1993: 453-465
1992
1		Felice Balarin, Alberto L. Sangiovanni-Vincentelli: A Verification Strategy for Timing-Constrained Systems. CAV 1992: 151-163

Coauthor Index

1	Adnan Aziz	[5] [6] [9] [10] [11] [26]
2	Laxmi N. Bhuyan	[43]
3	Robert K. Brayton	[5] [6] [9] [10] [26]
4	Xi Chen	[38] [39] [40] [41] [43] [45] [46] [47] [50]
5	Szu-Tsung Cheng	[6]
6	Eric Cheung	[51]
7	Massimiliano Chiodo	[16] [20] [22]
8	M. D. DiBenedetto	[10]
9	Paolo Giusto	[20]
10	Ramin Hojati	[6]
11	Harry Hsieh	[13] [20] [23] [28] [30] [37] [38] [39] [40] [41] [43] [45] [46] [47] [50] [51]
12	Attila Jurecska	[13] [16] [20]
13	Timothy Kam	[6]
14	Sriram C. Krishnan	[6]
15	Luciano Lavagno	[13] [16] [17] [20] [28] [30] [34] [35] [36] [37]
16	Yan Luo	[43]
17	Praveen K. Murthy	[17]
18	Marco Di Natale	[29] [31]
19	Claudio Passerone	[34] [35] [36] [37] [44]
20	Roberto Passerone	[48] [49]
21	Alessandro Pinto	[44]
22	Rajeev K. Ranjan	[6]
23	Alexander Saldanha	[10]
24	Alberto L. Sangiovanni-Vincentelli	[1] [3] [4] [5] [6] [7] [8] [9] [13] [15] [16] [17] [20] [26] [28] [29] [30] [31] [35] [36] [37] [42] [44] [47]
25	Ellen Sentovich (Ellen M. Sentovich)	[20]
26	Marco Sgroi	[35]
27	Thomas R. Shiple	[6]
28	Vigyan Singhal	[5] [6] [11]
29	Kei Suzuki	[20]
30	Bassam Tabbara	[16]
31	Serdar Tasiran	[6]
32	Huey-Yih Wang	[6]
33	Yosinori Watanabe	[34] [35] [36] [37] [38] [39] [40] [41] [42]
34	Wei Wu	[45] [50]
35	Guang Yang	[36] [42] [47]
36	Jun Yang	[45] [50]
37	Gary York	[2]
38	Jia Yu	[45] [50]

Colors in the list of coauthors