Vaughn Betz

2008
18	EE	Adrian Ludwin, Vaughn Betz, Ketan Padalia: High-quality, deterministic parallel placement for FPGAs on commodity hardware. FPGA 2008: 14-23
17	EE	Ryan Fung, Vaughn Betz, William Chow: Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 686-697 (2008)
2007
16	EE	Russell Tessier, Vaughn Betz, David Neto, Aaron Egier, Thiagaraja Gopalsamy: Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 278-290 (2007)
2006
15	EE	Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy: Power-aware RAM mapping for FPGA embedded memory blocks. FPGA 2006: 189-198
2005
14	EE	David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose: The Stratix II logic and routing architecture. FPGA 2005: 14-20
2004
13	EE	Ryan Fung, Vaughn Betz, William Chow: Simultaneous short-path and long-path timing optimization for FPGAs. ICCAD 2004: 838-845
2003
12	EE	David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose: The StratixTM routing and logic architecture. FPGA 2003: 12-20
2000
11	EE	Vaughn Betz, Jonathan Rose: Automatic generation of FPGA routing architectures from high-level descriptions. FPGA 2000: 175-184
10	EE	Alexander Marquardt, Vaughn Betz, Jonathan Rose: Timing-driven placement for FPGAs. FPGA 2000: 203-213
9	EE	Alexander Marquardt, Vaughn Betz, Jonathan Rose: Speed and area tradeoffs in cluster-based FPGA architectures. IEEE Trans. VLSI Syst. 8(1): 84-93 (2000)
1999
8	EE	Alexander Marquardt, Vaughn Betz, Jonathan Rose: Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density. FPGA 1999: 37-46
7	EE	Vaughn Betz, Jonathan Rose: FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. FPGA 1999: 59-68
1998
6	EE	Jordan S. Swartz, Vaughn Betz, Jonathan Rose: A Fast Routability-Driven Router for FPGAs. FPGA 1998: 140-149
5	EE	Vaughn Betz, Jonathan Rose: How Much Logic Should Go in an FPGA Logic Block? IEEE Design & Test of Computers 15(1): 10-15 (1998)
4	EE	Vaughn Betz, Jonathan Rose: Effect of the prefabricated routing track distribution on FPGA area-efficiency. IEEE Trans. VLSI Syst. 6(3): 445-456 (1998)
1997
3		Vaughn Betz, Jonathan Rose: VPR: A new packing, placement and routing tool for FPGA research. FPL 1997: 213-222
1996
2	EE	Vaughn Betz, Jonathan Rose: Directional bias and non-uniformity in FPGA global routing architectures. ICCAD 1996: 652-659
1995
1	EE	Vaughn Betz, Jonathan Rose: Using Architectural ``Families'' to Increase FPGA Speed and Density. FPGA 1995: 10-16

Coauthor Index

1	Elias Ahmed	[14]
2	Gregg Baeckler	[14]
3	Mark Bourgeault	[14]
4	David Cashman	[14]
5	William Chow	[13] [17]
6	Richard Cliff	[12] [14]
7	Aaron Egier	[16]
8	Ryan Fung	[13] [17]
9	David R. Galloway	[14]
10	Thiagaraja Gopalsamy	[15] [16]
11	Michael Hutton (Michael D. Hutton, Mike Hutton)	[14]
12	David Jefferson	[12]
13	Christopher Lane	[12] [14]
14	Andy Lee	[12] [14]
15	Paul Leventis	[12] [14]
16	David M. Lewis	[12] [14]
17	Adrian Ludwin	[18]
18	Alexander Marquardt	[8] [9] [10]
19	Sandy Marquardt	[12] [14]
20	Cameron McClintock	[12] [14]
21	David Neto	[15] [16]
22	Ketan Padalia	[14] [18]
23	Bruce Pedersen	[12] [14]
24	Giles Powell	[12] [14]
25	Boris Ratchev	[14]
26	Srinivas Reddy	[12] [14]
27	Jonathan Rose	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [14]
28	Jay Schleicher	[14]
29	Kevin Stevens	[14]
30	Jordan S. Swartz	[6]
31	Russell Tessier	[15] [16]
32	Chris Wysocki	[12]
33	Richard Yuan	[14]