Honghua Yang
List of publications from the DBLP Bibliography Server - FAQ
2008 | ||
---|---|---|
30 | EE | Hannah Honghua Yang, Martin D. F. Wong: Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach. Encyclopedia of Algorithms 2008 |
2007 | ||
29 | EE | Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng: Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 645-658 (2007) |
28 | EE | Hsun-Cheng Lee, Yao-Wen Chang, Hannah Honghua Yang: MBast-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1430-1444 (2007) |
2006 | ||
27 | EE | Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng: Integrating dynamic thermal via planning with 3D floorplanning algorithm. ISPD 2006: 178-185 |
26 | EE | Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani: Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. ACM Trans. Design Autom. Electr. Syst. 11(2): 325-345 (2006) |
2005 | ||
25 | EE | Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong: Microarchitecture evaluation with floorplanning and interconnect pipelining. ASP-DAC 2005: 8-15 |
24 | EE | Guowu Yang, Xiaoyu Song, Hannah Honghua Yang, Fei Xie: A Theoretical Upper Bound for IP-Based Floorplanning. COCOON 2005: 411-419 |
2004 | ||
23 | Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu: Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. ISCAS (5) 2004: 81-84 | |
22 | EE | Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang: Constrained floorplanning using network flows. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 572-580 (2004) |
2003 | ||
21 | EE | Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang: Multilevel floorplanning/placement for large-scale modules using B*-trees. DAC 2003: 812-817 |
20 | EE | Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang: Constrained "Modern" Floorplanning. ISPD 2003: 128-135 |
19 | EE | Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani: Integrated floorplanning with buffer/channel insertion for bus-based designs. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 730-741 (2003) |
2002 | ||
18 | EE | Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani: Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. ISPD 2002: 56-61 |
2001 | ||
17 | EE | Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang: Faster and more accurate wiring evaluation in interconnect-centric floorplanning. ACM Great Lakes Symposium on VLSI 2001: 62-67 |
16 | EE | Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang: On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 800-807 (2001) |
2000 | ||
15 | EE | Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang: Slicing floorplans with range constraint. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 272-278 (2000) |
1999 | ||
14 | EE | Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani: Integrated floorplanning and interconnect planning. ICCAD 1999: 354-357 |
13 | EE | Jeremy Casas, Hannah Honghua Yang, Manpreet Khaira, Mandar Joshi, Thomas Tetzlaff, Steve W. Otto, Erik Seligman: Logic Verification of Very Large Circuits Using Shark. VLSI Design 1999: 310-317 |
12 | EE | Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang: Slicing floorplans with boundary constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1385-1389 (1999) |
1998 | ||
11 | EE | Hannah Honghua Yang, Martin D. F. Wong: Optimal min-area min-cut replication in partitioned circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1175-1183 (1998) |
1997 | ||
10 | Vijaya Ramachandran, Honghua Yang: An Efficient Parallel Algorithm for the Layered Planar Monotone Circuit Value Problem. Algorithmica 18(3): 384-404 (1997) | |
9 | EE | Hannah Honghua Yang, Martin D. F. Wong: Circuit clustering for delay minimization under area and pin constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 976-986 (1997) |
1996 | ||
8 | EE | Hannah Honghua Yang, Martin D. F. Wong: Balanced partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1533-1540 (1996) |
7 | Vijaya Ramachandran, Honghua Yang: An Efficient Parallel Algorithm for the General Planar Monotone Circuit Value Problem. SIAM J. Comput. 25(2): 312-339 (1996) | |
1995 | ||
6 | EE | Hannah Honghua Yang, D. F. Wong: New algorithms for min-cut replication in partitioned circuits. ICCAD 1995: 216-222 |
1994 | ||
5 | EE | Hannah Honghua Yang, D. F. Wong: Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. ICCAD 1994: 150-155 |
4 | EE | Honghua Yang, D. F. Wong: Efficient network flow based min-cut balanced partitioning. ICCAD 1994: 50-55 |
3 | Vijaya Ramachandran, Honghua Yang: An Efficient Parallel Algorithm for the General Planar Monotone Circuit Value Problem. SODA 1994: 622-631 | |
2 | Vijaya Ramachandran, Honghua Yang: Finding the Closed Partition of a Planar Graph. Algorithmica 11(5): 443-468 (1994) | |
1993 | ||
1 | Vijaya Ramachandran, Honghua Yang: An Efficient Parallel Algorithm for the Layered Planar Monotone Circuit Value Problem. ESA 1993: 321-332 |