dblp.uni-trier.dewww.uni-trier.de

Srinivasa R. Sridhara

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2008
9EESrinivasa R. Sridhara, Ganesh Balamurugan, Naresh R. Shanbhag: Joint Equalization and Coding for On-Chip Bus Communication. IEEE Trans. VLSI Syst. 16(3): 314-318 (2008)
2007
8EESrinivasa R. Sridhara, Naresh R. Shanbhag: Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 977-982 (2007)
2005
7EESrinivasa R. Sridhara, Naresh R. Shanbhag: A low-power bus design using joint repeater insertion and coding. ISLPED 2005: 99-102
6EESrinivasa R. Sridhara, Naresh R. Shanbhag, Ganesh Balamurugan: Joint Equalization and Coding for On-Chip Bus Communication. ISQED 2005: 642-647
5EESrinivasa R. Sridhara, Naresh R. Shanbhag: Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes. VLSI Design 2005: 417-422
4EESrinivasa R. Sridhara, Naresh R. Shanbhag: Coding for system-on-chip networks: a unified framework. IEEE Trans. VLSI Syst. 13(6): 655-667 (2005)
2004
3EESrinivasa R. Sridhara, Naresh R. Shanbhag: Coding for system-on-chip networks: a unified framework. DAC 2004: 103-106
2EESrinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag: Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses. ICCD 2004: 12-17
1 Byonghyo Shim, Srinivasa R. Sridhara, Naresh R. Shanbhag: Reliable low-power digital signal processing via reduced precision redundancy. IEEE Trans. VLSI Syst. 12(5): 497-510 (2004)

Coauthor Index

1Arshad Ahmed [2]
2Ganesh Balamurugan [6] [9]
3Naresh R. Shanbhag [1] [2] [3] [4] [5] [6] [7] [8] [9]
4Byonghyo Shim [1]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)