| 2007 |
|---|
| 10 | EE | Salvador Manich,
L. Garcia-Deiros,
Joan Figueras:
Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2046-2058 (2007) |
| 2004 |
|---|
| 9 | EE | Salvador Manich,
L. García,
L. Balado,
E. Lupon,
Josep Rius,
Rosa Rodríguez-Montañés,
Joan Figueras:
BIST Technique by Equally Spaced Test Vector Sequences.
VTS 2004: 206-216 |
| 8 | EE | Marcelino B. Santos,
Isabel C. Teixeira,
João Paulo Teixeira,
Salvador Manich,
L. Balado,
Joan Figueras:
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level.
J. Electronic Testing 20(4): 345-355 (2004) |
| 2003 |
|---|
| 7 | EE | Josep Rius,
Alejandro Peidro,
Salvador Manich,
Rosa Rodriguez-Sánchez:
Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results.
PATMOS 2003: 80-89 |
| 2002 |
|---|
| 6 | EE | Marcelino B. Santos,
Isabel C. Teixeira,
João Paulo Teixeira,
Salvador Manich,
Rosa Rodríguez-Montañés,
Joan Figueras:
RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST.
ITC 2002: 814-823 |
| 2000 |
|---|
| 5 | EE | Salvador Manich,
A. Gabarró,
M. Lopez,
Joan Figueras,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
P. Teixeira,
M. Santos:
Low Power BIST by Filtering Non-Detecting Vectors.
J. Electronic Testing 16(3): 193-202 (2000) |
| 1999 |
|---|
| 4 | EE | Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Joan Figueras,
Salvador Manich,
P. Teixeira,
M. Santos:
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.
ISCAS (1) 1999: 110-113 |
| 1997 |
|---|
| 3 | EE | Salvador Manich,
Joan Figueras:
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model.
ED&TC 1997: 597-602 |
| 2 | EE | Michael Nicolaidis,
Ricardo de Oliveira Duarte,
Salvador Manich,
Joan Figueras:
Fault-Secure Parity Prediction Arithmetic Operators.
IEEE Design & Test of Computers 14(2): 60-71 (1997) |
| 1996 |
|---|
| 1 | EE | Salvador Manich,
Michael Nicolaidis,
Joan Figueras:
Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring.
VTS 1996: 124-129 |
