2007 |
18 | EE | Hao Fang,
Chenguang Tong,
Bo Yao,
Xiaodi Song,
Xu Cheng:
CacheCompress: a novel approach for test data compression with cache for IP embedded cores.
ICCAD 2007: 509-512 |
17 | EE | Ling Zhang,
Hongyu Chen,
Bo Yao,
Kevin Hamilton,
Chung-Kuan Cheng:
Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals.
ISQED 2007: 251-256 |
16 | EE | Bo Yao,
Qingchun Chen:
On the Temporal-Spatial Correlation Based Fault-Tolerant Dynamic Event Region Detection Scheme in Wireless Sensor Networks.
MSN 2007: 511-523 |
15 | EE | Shuo Zhou,
Bo Yao,
Hongyu Chen,
Yi Zhu,
Michael Hutton,
Truman Collins,
Sridhar Srinivasan,
Nan-Chi Chou,
Peter Suaris,
Chung-Kuan Cheng:
Efficient Timing Analysis With Known False Paths Using Biclique Covering.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 959-969 (2007) |
2006 |
14 | EE | Shuo Zhou,
Bo Yao,
Hongyu Chen,
Yi Zhu,
Chung-Kuan Cheng,
Michael Hutton:
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths.
ASP-DAC 2006: 73-78 |
2005 |
13 | EE | Shuo Zhou,
Bo Yao,
Jianhua Liu,
Chung-Kuan Cheng:
Integrated algorithmic logical and physical design of integer multiplier.
ASP-DAC 2005: 1014-1017 |
12 | | Shuo Zhou,
Bo Yao,
Hongyu Chen,
Yi Zhu,
Chung-Kuan Cheng,
Michael Hutton,
Truman Collins,
Sridhar Srinivasan,
Nan-Chi Chou,
Peter Suaris:
Improving the efficiency of static timing analysis with false paths.
ICCAD 2005: 527-531 |
11 | EE | Bo Yao,
Hongyu Chen,
Chung-Kuan Cheng,
Nan-Chi Chou,
Lung-Tien Liu,
Peter Suaris:
Unified quadratic programming approach for mixed mode placement.
ISPD 2005: 193-199 |
10 | EE | Hongyu Chen,
Chung-Kuan Cheng,
Andrew B. Kahng,
Ion I. Mandoiu,
Qinke Wang,
Bo Yao:
The Y architecture for on-chip interconnect: analysis and methodology.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 588-599 (2005) |
2004 |
9 | EE | Makoto Mori,
Hongyu Chen,
Bo Yao,
Chung-Kuan Cheng:
A multiple level network approach for clock skew minimization with process variations.
ASP-DAC 2004: 263-268 |
2003 |
8 | EE | Zhengyong Zhu,
Bo Yao,
Chung-Kuan Cheng:
Power network analysis using an adaptive algebraic multigrid approach.
DAC 2003: 105-108 |
7 | EE | Hongyu Chen,
Chung-Kuan Cheng,
Nan-Chi Chou,
Andrew B. Kahng,
John F. MacDonald,
Peter Suaris,
Bo Yao,
Zhengyong Zhu:
An algebraic multigrid solver for analytical placement with layout based clustering.
DAC 2003: 794-799 |
6 | EE | Hongyu Chen,
Chung-Kuan Cheng,
Andrew B. Kahng,
Ion I. Mandoiu,
Qinke Wang,
Bo Yao:
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology.
ICCAD 2003: 13-20 |
5 | EE | Feng Zhou,
Esther Y. Cheng,
Bo Yao,
Chung-Kuan Cheng,
Ronald L. Graham:
A hierarchical three-way interconnect architecture for hexagonal processors.
SLIP 2003: 133-139 |
4 | EE | Bo Yao,
Hongyu Chen,
Chung-Kuan Cheng,
Ronald L. Graham:
Floorplan representations: Complexity and connections.
ACM Trans. Design Autom. Electr. Syst. 8(1): 55-80 (2003) |
2002 |
3 | EE | Esther Y. Cheng,
Feng Zhou,
Bo Yao,
Chung-Kuan Cheng,
Ronald L. Graham:
Balancing the Interconnect Topology for Arrays of Processors between Cost and Power.
ICCD 2002: 180-186 |
2 | EE | Hongyu Chen,
Bo Yao,
Feng Zhou,
Chung-Kuan Cheng:
Physical Planning Of On-Chip Interconnect Architectures.
ICCD 2002: 30-35 |
2001 |
1 | EE | Bo Yao,
Hongyu Chen,
Chung-Kuan Cheng,
Ronald L. Graham:
Revisiting floorplan representations.
ISPD 2001: 138-143 |