B. P. Harish

List of publications from the DBLP Bibliography Server - FAQ

2007

2 EE B. P. Harish, Navakanta Bhat, Mahesh B. Patil: Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs. ICCTA 2007: 94-98

1 EE B. P. Harish, Navakanta Bhat, Mahesh B. Patil: On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 606-614 (2007)

2007
2	EE	B. P. Harish, Navakanta Bhat, Mahesh B. Patil: Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs. ICCTA 2007: 94-98
1	EE	B. P. Harish, Navakanta Bhat, Mahesh B. Patil: On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 606-614 (2007)

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