| 2007 |
|---|
| 8 | EE | Ahmad A. Al-Yamani,
Narendra Devta-Prasanna,
Arun Gunda:
Systematic Scan Reconfiguration.
ASP-DAC 2007: 738-743 |
| 7 | EE | Ahmad A. Al-Yamani,
Narendra Devta-Prasanna,
Erik Chmelar,
M. Grinchuk,
Arun Gunda:
Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 907-918 (2007) |
| 2006 |
|---|
| 6 | EE | Narendra Devta-Prasanna,
Arun Gunda,
P. Krishnamurthy,
Sudhakar M. Reddy,
Irith Pomeranz:
Test Generation for Open Defects in CMOS Circuits.
DFT 2006: 41-49 |
| 5 | EE | Narendra Devta-Prasanna,
Arun Gunda,
P. Krishnamurthy,
Sudhakar M. Reddy,
Irith Pomeranz:
A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults.
European Test Symposium 2006: 185-192 |
| 2005 |
|---|
| 4 | EE | Narendra Devta-Prasanna,
Sudhakar M. Reddy,
Arun Gunda,
P. Krishnamurthy,
Irith Pomeranz:
Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions.
Asian Test Symposium 2005: 202-207 |
| 3 | EE | Ahmad A. Al-Yamani,
Narendra Devta-Prasanna,
Arun Gunda:
Should Illinois-Scan Based Architectures be Centralized or Distributed?
DFT 2005: 406-414 |
| 2 | EE | Narendra Devta-Prasanna,
Arun Gunda,
P. Krishnamurthy,
Sudhakar M. Reddy,
Irith Pomeranz:
A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals.
ICCD 2005: 471-474 |
| 1995 |
|---|
| 1 | | Kaushik De,
Arun Gunda:
Failure Analysis for Full-Scan Circuits.
ITC 1995: 636-645 |
