| 2009 |
|---|
| 140 | EE | Renatas Jakushokas,
Eby G. Friedman:
Simultaneous shield and repeater insertion.
ACM Great Lakes Symposium on VLSI 2009: 15-20 |
| 139 | EE | Eby G. Friedman:
Design challenges in high performance three-dimensional circuits.
ACM Great Lakes Symposium on VLSI 2009: 281-282 |
| 138 | EE | Inna Vaisband,
Ran Ginosar,
Avinoam Kolodny,
Eby G. Friedman:
Power efficient tree-based crosslinks for skew reduction.
ACM Great Lakes Symposium on VLSI 2009: 285-290 |
| 137 | EE | Emre Salman,
Renatas Jakushokas,
Eby G. Friedman,
Radu M. Secareanu,
Olin L. Hartin:
Contact merging algorithm for efficient substrate noise analysis in large scale circuits.
ACM Great Lakes Symposium on VLSI 2009: 9-14 |
| 136 | EE | Jonathan Rosenfeld,
Eby G. Friedman:
On-chip DC-DC converters for three-dimensional ICs.
ISQED 2009: 759-764 |
| 2008 |
|---|
| 135 | EE | Emre Salman,
Eby G. Friedman,
Radu M. Secareanu,
Olin L. Hartin:
Equivalent rise time for resonance in power/ground noise estimation.
ISCAS 2008: 2422-2425 |
| 134 | EE | Guoqing Chen,
Eby G. Friedman:
Transient simulation of on-chip transmission lines via exact pole extraction.
ISCAS 2008: 2757-2760 |
| 133 | EE | Emre Salman,
Renatas Jakushokas,
Eby G. Friedman,
Radu M. Secareanu,
Olin L. Hartin:
Input port reduction for efficient substrate extraction in large scale IC's.
ISCAS 2008: 376-379 |
| 132 | EE | Ioannis Savidis,
Eby G. Friedman:
Electrical modeling and characterization of 3-D vias.
ISCAS 2008: 784-787 |
| 131 | EE | Emre Salman,
Eby G. Friedman,
Radu M. Secareanu,
Olin L. Hartin:
Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates.
ISQED 2008: 261-266 |
| 130 | EE | Arkadiy Morgenshtein,
Eby G. Friedman,
Ran Ginosar,
Avinoam Kolodny:
Timing optimization in logic with interconnect.
SLIP 2008: 19-26 |
| 129 | EE | Alexander Lavzin,
Mücahit Kozak,
Eby G. Friedman:
A higher-order mismatch-shaping method for multi-bit Sigma-Delta Modulators.
SoCC 2008: 267-270 |
| 128 | EE | Selcuk Kose,
Emre Salman,
Zeljko Ignjatovic,
Eby G. Friedman:
Pseudo-random clocking to enhance signal integrity.
SoCC 2008: 47-50 |
| 127 | EE | Mikhail Popovich,
Eby G. Friedman:
Nanoscale on-chip decoupling capacitors.
SoCC 2008: 51-54 |
| 126 | EE | Mikhail Popovich,
Eby G. Friedman,
Radu M. Secareanu,
Olin L. Hartin:
Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs.
IEEE Trans. VLSI Syst. 16(12): 1717-1721 (2008) |
| 125 | EE | Mikhail Popovich,
Michael Sotman,
Avinoam Kolodny,
Eby G. Friedman:
Effective Radii of On-Chip Decoupling Capacitors.
IEEE Trans. VLSI Syst. 16(7): 894-907 (2008) |
| 124 | EE | Mikhail Popovich,
Eby G. Friedman,
Michael Sotman,
Avinoam Kolodny:
On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits.
IEEE Trans. VLSI Syst. 16(7): 908-921 (2008) |
| 123 | EE | Vasilis F. Pavlidis,
Eby G. Friedman:
Timing-driven via placement heuristics for three-dimensional ICs.
Integration 41(4): 489-508 (2008) |
| 2007 |
|---|
| 122 | EE | Mikhail Popovich,
Eby G. Friedman,
Radu M. Secareanu,
Olin L. Hartin:
Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs.
ICCAD 2007: 811-816 |
| 121 | EE | Emre Salman,
Eby G. Friedman,
Radu M. Secareanu,
Olin L. Hartin:
Substrate Noise Reduction Based On Noise Aware Cell Design.
ISCAS 2007: 3227-3230 |
| 120 | EE | Jonathan Rosenfeld,
Eby G. Friedman:
Quasi-Resonant Interconnects: A Low Power Design Methodology.
ISCAS 2007: 641-644 |
| 119 | EE | Vasilis F. Pavlidis,
Eby G. Friedman:
3-D Topologies for Networks-on-Chip.
IEEE Trans. VLSI Syst. 15(10): 1081-1090 (2007) |
| 118 | EE | Jonathan Rosenfeld,
Eby G. Friedman:
Design Methodology for Global Resonant H-Tree Clock Distribution Networks.
IEEE Trans. VLSI Syst. 15(2): 135-148 (2007) |
| 117 | EE | Emre Salman,
Ali Dasdan,
Feroze Taraporevala,
Kayhan Küçükçakar,
Eby G. Friedman:
Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1114-1125 (2007) |
| 116 | EE | Guoqing Chen,
Hui Chen,
Mikhail Haurylau,
Nicholas Nelson,
David H. Albonesi,
Philippe M. Fauchet,
Eby G. Friedman:
Predictions of CMOS compatible on-chip optical interconnect.
Integration 40(4): 434-446 (2007) |
| 115 | EE | Magdy A. El-Moursy,
Eby G. Friedman:
Wire shaping of RLC interconnects.
Integration 40(4): 461-472 (2007) |
| 2006 |
|---|
| 114 | EE | Mikhail Popovich,
Eby G. Friedman,
Michael Sotman,
Avinoam Kolodny,
Radu M. Secareanu:
Maximum effective distance of on-chip decoupling capacitors in power distribution grids.
ACM Great Lakes Symposium on VLSI 2006: 173-179 |
| 113 | EE | Jonathan Rosenfeld,
Eby G. Friedman:
Sensitivity evaluation of global resonant H-tree clock distribution networks.
ACM Great Lakes Symposium on VLSI 2006: 192-197 |
| 112 | EE | Jonathan Rosenfeld,
Eby G. Friedman:
Design methodology for global resonant H-tree clock distribution networks.
ISCAS 2006 |
| 111 | EE | Guoqing Chen,
Eby G. Friedman:
Effective capacitance of RLC loads for estimating short-circuit power.
ISCAS 2006 |
| 110 | EE | Michael Sotman,
Avinoam Kolodny,
Mikhail Popovich,
Eby G. Friedman:
On-die decoupling capacitance: frequency domain analysis of activity radius.
ISCAS 2006 |
| 109 | EE | Magdy A. El-Moursy,
Eby G. Friedman:
Optimum wire tapering for minimum power dissipation in RLC interconnects.
ISCAS 2006 |
| 108 | EE | Vasilis F. Pavlidis,
Eby G. Friedman:
Via placement for minimum interconnect delay in three-dimensional (3D) circuits.
ISCAS 2006 |
| 107 | EE | Emre Salman,
Eby G. Friedman,
Ali Dasdan,
Feroze Taraporevala,
Kayhan Küçükçakar:
Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times.
ISQED 2006: 159-164 |
| 106 | EE | Guoqing Chen,
Eby G. Friedman:
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints.
IEEE Trans. VLSI Syst. 14(2): 161-172 (2006) |
| 105 | EE | Mikhail Popovich,
Eby G. Friedman:
Decoupling capacitors for multi-voltage power distribution systems.
IEEE Trans. VLSI Syst. 14(3): 217-228 (2006) |
| 104 | EE | Junmou Zhang,
Eby G. Friedman:
Crosstalk modeling for coupled RLC interconnects with application to shield insertion.
IEEE Trans. VLSI Syst. 14(6): 641-646 (2006) |
| 103 | EE | Boris D. Andreev,
Edward L. Titlebaum,
Eby G. Friedman:
Sizing CMOS inverters with Miller Effect and Threshold voltage Variations.
Journal of Circuits, Systems, and Computers 15(3): 437-454 (2006) |
| 2005 |
|---|
| 102 | EE | Mikhail Popovich,
Eby G. Friedman,
Michael Sotman,
Avinoam Kolodny:
On-chip power distribution grids with multiple supply voltages for high performance integrated circuits.
ACM Great Lakes Symposium on VLSI 2005: 2-7 |
| 101 | EE | Vasilis F. Pavlidis,
Eby G. Friedman:
Interconnect delay minimization through interlayer via placement in 3-D ICs.
ACM Great Lakes Symposium on VLSI 2005: 20-25 |
| 100 | EE | Volkan Kursun,
Gerhard Schrom,
Vivek De,
Eby G. Friedman,
Siva Narendra:
Cascode buffer for monolithic voltage conversion operating at high input supply voltages.
ISCAS (1) 2005: 464-467 |
| 99 | EE | Guoqing Chen,
Eby G. Friedman:
Low power repeaters driving RLC interconnects with delay and bandwidth constraints.
ISCAS (1) 2005: 596-599 |
| 98 | EE | Radu M. Secareanu,
S. K. Banerjee,
Olin L. Hartin,
Francisco V. Fernández,
Eby G. Friedman:
Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment.
ISCAS (1) 2005: 612-615 |
| 97 | EE | Mikhail Popovich,
Eby G. Friedman:
Noise coupling in multi-voltage power distribution systems with decoupling capacitors.
ISCAS (1) 2005: 620-623 |
| 96 | EE | Guoqing Chen,
Hui Chen,
Mikhail Haurylau,
Nicholas Nelson,
Philippe M. Fauchet,
Eby G. Friedman,
David H. Albonesi:
Electrical and optical on-chip interconnects in scaled microprocessors.
ISCAS (3) 2005: 2514-2517 |
| 95 | EE | Guoqing Chen,
Eby G. Friedman:
A Fourier series-based RLC interconnect model for periodic signals.
ISCAS (4) 2005: 4126-4129 |
| 94 | EE | Mikhail Popovich,
Eby G. Friedman:
Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems.
ISQED 2005: 334-339 |
| 93 | EE | Guoqing Chen,
Hui Chen,
Mikhail Haurylau,
Nicholas Nelson,
Philippe M. Fauchet,
Eby G. Friedman,
David H. Albonesi:
Predictions of CMOS compatible on-chip optical interconnect.
SLIP 2005: 13-20 |
| 92 | EE | Magdy A. El-Moursy,
Eby G. Friedman:
Shielding effect of on-chip interconnect inductance.
IEEE Trans. VLSI Syst. 13(3): 396-400 (2005) |
| 91 | EE | Magdy A. El-Moursy,
Eby G. Friedman:
Exponentially tapered H-tree clock distribution networks.
IEEE Trans. VLSI Syst. 13(8): 971-975 (2005) |
| 90 | EE | Guoqing Chen,
Eby G. Friedman:
An RLC interconnect model based on fourier analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 170-183 (2005) |
| 89 | EE | Volkan Kursun,
Vivek De,
Eby G. Friedman,
Siva G. Narendra:
Monolithic voltage conversion in low-voltage CMOS technologies.
Microelectronics Journal 36(9): 863-867 (2005) |
| 2004 |
|---|
| 88 | EE | Junmou Zhang,
Simon R. Cooper,
Andrew R. LaPietra,
Michael W. Mattern,
Robert M. Guidash,
Eby G. Friedman:
A low power thyristor-based CMOS programmable delay element.
ISCAS (1) 2004: 769-772 |
| 87 | | Volkan Kursun,
Eby G. Friedman:
Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage.
ISCAS (2) 2004: 417-420 |
| 86 | | Junmou Zhang,
Eby G. Friedman:
Decoupling technique and crosstalk analysis for coupled RLC interconnects.
ISCAS (2) 2004: 521-524 |
| 85 | | Junmou Zhang,
Eby G. Friedman:
Effect of shield insertion on reducing crosstalk noise between coupled interconnects.
ISCAS (2) 2004: 529-532 |
| 84 | | Magdy A. El-Moursy,
Eby G. Friedman:
Exponentially tapered H-tree clock distribution networks.
ISCAS (2) 2004: 601-604 |
| 83 | | Volkan Kursun,
Eby G. Friedman:
Forward body biased keeper for enhanced noise immunity in domino logic circuits.
ISCAS (2) 2004: 917-920 |
| 82 | | Mücahit Kozak,
Eby G. Friedman:
Design and simulation of Fractional-N PLL frequency synthesizers.
ISCAS (4) 2004: 780-783 |
| 81 | | Boris D. Andreev,
Edward L. Titlebaum,
Eby G. Friedman:
Low power flexible Rake receivers for WCDMA.
ISCAS (4) 2004: 97-100 |
| 80 | EE | Volkan Kursun,
Eby G. Friedman:
Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits.
ISQED 2004: 104-109 |
| 79 | EE | Volkan Kursun,
Siva Narendra,
Vivek De,
Eby G. Friedman:
High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process.
ISQED 2004: 517-521 |
| 78 | EE | Dimitrios Velenis,
Eby G. Friedman:
Buffer Sizing for Crosstalk Induced Delay Uncertainty.
PATMOS 2004: 750-759 |
| 77 | | Radu M. Secareanu,
Scott Warner,
Scott Seabridge,
Cathie Burke,
Juan Becerra,
Thomas E. Watrobski,
Christopher Morton,
William Staub,
Thomas Tellier,
Ivan S. Kourtev,
Eby G. Friedman:
Substrate coupling in digital circuits in mixed-signal smart-power systems.
IEEE Trans. VLSI Syst. 12(1): 67-78 (2004) |
| 76 | EE | Andrey V. Mezhiba,
Eby G. Friedman:
Impedance characteristics of power distribution grids in nanoscale integrated circuits.
IEEE Trans. VLSI Syst. 12(11): 1148-1155 (2004) |
| 75 | EE | Magdy A. El-Moursy,
Eby G. Friedman:
Power characteristics of inductive interconnect.
IEEE Trans. VLSI Syst. 12(12): 1295-1306 (2004) |
| 74 | | Andrey V. Mezhiba,
Eby G. Friedman:
Scaling trends of on-chip power distribution noise.
IEEE Trans. VLSI Syst. 12(4): 386-394 (2004) |
| 73 | | Volkan Kursun,
Eby G. Friedman:
Sleep switch dual threshold Voltage domino logic with reduced standby leakage current.
IEEE Trans. VLSI Syst. 12(5): 485-496 (2004) |
| 72 | EE | Magdy A. El-Moursy,
Eby G. Friedman:
Optimum wire sizing of RLC interconnect with repeaters .
Integration 38(2): 205-225 (2004) |
| 71 | EE | Boris D. Andreev,
Edward L. Titlebaum,
Eby G. Friedman:
Complex +/-1 Multiplier Based on Signed-Binary Transformations.
VLSI Signal Processing 38(1): 13-24 (2004) |
| 2003 |
|---|
| 70 | EE | Magdy A. El-Moursy,
Eby G. Friedman:
Shielding effect of on-chip interconnect inductance.
ACM Great Lakes Symposium on VLSI 2003: 165-170 |
| 69 | EE | Boris D. Andreev,
Edward L. Titlebaum,
Eby G. Friedman:
Orthogonal code generator for 3G wireless transceivers.
ACM Great Lakes Symposium on VLSI 2003: 229-232 |
| 68 | EE | Magdy A. El-Moursy,
Eby G. Friedman:
Optimum wire sizing of RLC interconnect with repeaters.
ACM Great Lakes Symposium on VLSI 2003: 27-32 |
| 67 | EE | Dimitrios Velenis,
Marios C. Papaefthymiou,
Eby G. Friedman:
Reduced Delay Uncertainty in High Performance Clock Distribution Networks.
DATE 2003: 10068-10075 |
| 66 | EE | Magdy A. El-Moursy,
Eby G. Friedman:
Inductive interconnect width optimization for low power.
ISCAS (5) 2003: 273-276 |
| 65 | EE | Andrey V. Mezhiba,
Eby G. Friedman:
Electrical characteristics of multi-layer power distribution grids.
ISCAS (5) 2003: 473-476 |
| 64 | EE | Volkan Kursun,
Siva Narendra,
Vivek De,
Eby G. Friedman:
Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization.
ISQED 2003: 279- |
| 63 | EE | Boris D. Andreev,
Edward L. Titlebaum,
Eby G. Friedman:
Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic.
IWSOC 2003: 70-75 |
| 62 | EE | David H. Albonesi,
Rajeev Balasubramonian,
Steve Dropsho,
Sandhya Dwarkadas,
Eby G. Friedman,
Michael C. Huang,
Volkan Kursun,
Grigorios Magklis,
Michael L. Scott,
Greg Semeraro,
Pradip Bose,
Alper Buyuktosunoglu,
Peter W. Cook,
Stanley Schuster:
Dynamically Tuning Processor Resources with Adaptive Processing.
IEEE Computer 36(12): 49-58 (2003) |
| 61 | EE | Volkan Kursun,
Siva G. Narendra,
Vivek De,
Eby G. Friedman:
Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor.
IEEE Trans. VLSI Syst. 11(3): 514-522 (2003) |
| 60 | EE | Volkan Kursun,
Eby G. Friedman:
Domino logic with variable threshold voltage keeper.
IEEE Trans. VLSI Syst. 11(6): 1080-1093 (2003) |
| 59 | EE | Yehea I. Ismail,
Eby G. Friedman:
On the Extraction of On-Chip Inductance.
Journal of Circuits, Systems, and Computers 12(1): 31-40 (2003) |
| 2002 |
|---|
| 58 | EE | Andrey V. Mezhiba,
Eby G. Friedman:
Properties of on-chip inductive current loops.
ACM Great Lakes Symposium on VLSI 2002: 12-17 |
| 57 | EE | Volkan Kursun,
Eby G. Friedman:
Low swing dual threshold voltage domino logic.
ACM Great Lakes Symposium on VLSI 2002: 47-52 |
| 56 | EE | Boris D. Andreev,
Eby G. Friedman,
Edward L. Titlebaum:
Efficient implementation of a complex ±1 multiplier.
ACM Great Lakes Symposium on VLSI 2002: 83-88 |
| 55 | EE | Andrey V. Mezhiba,
Eby G. Friedman:
Inductance/area/resistance tradeoffs in high performance power distribution grids.
ISCAS (1) 2002: 101-104 |
| 54 | EE | Weize Xu,
Eby G. Friedman:
A substrate noise circuit for accurately testing mixed-signal ICs.
ISCAS (1) 2002: 145-148 |
| 53 | EE | Roy Mader,
Eby G. Friedman,
Ami Litman,
Ivan S. Kourtev:
Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits.
ISCAS (1) 2002: 357-360 |
| 52 | EE | Andrey V. Mezhiba,
Eby G. Friedman:
Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits.
ISQED 2002: 316-321 |
| 51 | EE | Steve Dropsho,
Volkan Kursun,
David H. Albonesi,
Sandhya Dwarkadas,
Eby G. Friedman:
Managing static leakage energy in microprocessor functional units.
MICRO 2002: 321-332 |
| 50 | EE | Andrey V. Mezhiba,
Eby G. Friedman:
Scaling trends of on-chip Power distribution noise.
SLIP 2002: 47-53 |
| 49 | EE | Kevin T. Tang,
Eby G. Friedman:
Simultaneous switching noise in on-chip CMOS power distribution networks.
IEEE Trans. VLSI Syst. 10(4): 487-493 (2002) |
| 48 | EE | Andrey V. Mezhiba,
Eby G. Friedman:
Inductive properties of high-performance power distribution grids.
IEEE Trans. VLSI Syst. 10(6): 762-776 (2002) |
| 47 | EE | Yehea I. Ismail,
Eby G. Friedman:
DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 131-144 (2002) |
| 46 | EE | Xun Liu,
Marios C. Papaefthymiou,
Eby G. Friedman:
Retiming and clock scheduling for digital circuit optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 184-203 (2002) |
| 45 | EE | Dimitrios Velenis,
Kevin T. Tang,
Ivan S. Kourtev,
V. Adler,
F. Baez,
Eby G. Friedman:
Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling.
Journal of Circuits, Systems, and Computers 11(3): 231-246 (2002) |
| 44 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Inductance Effects in RLC Trees.
Journal of Circuits, Systems, and Computers 11(3): 305- (2002) |
| 2001 |
|---|
| 43 | EE | Dimitrios Velenis,
Eby G. Friedman,
Marios C. Papaefthymiou:
A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty.
ISCAS (4) 2001: 422-425 |
| 42 | EE | Kevin T. Tang,
Eby G. Friedman:
Estimation of transient voltage fluctuations in the CMOS-based power distribution networks.
ISCAS (5) 2001: 463-466 |
| 41 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Exploiting the on-chip inductance in high-speed clock distribution networks.
IEEE Trans. VLSI Syst. 9(6): 963-973 (2001) |
| 2000 |
|---|
| 40 | EE | Kevin T. Tang,
Eby G. Friedman:
Noise estimation due to signal activity for capacitively coupled CMOS logic gates.
ACM Great Lakes Symposium on VLSI 2000: 171-176 |
| 39 | EE | Radu M. Secareanu,
Eby G. Friedman:
Transparent repeaters.
ACM Great Lakes Symposium on VLSI 2000: 63-66 |
| 38 | EE | Yehea I. Ismail,
Eby G. Friedman:
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits.
IEEE Trans. VLSI Syst. 8(2): 195-206 (2000) |
| 37 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Equivalent Elmore delay for RLC trees.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 83-97 (2000) |
| 36 | EE | Kevin T. Tang,
Eby G. Friedman:
Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections.
Integration 29(2): 131-165 (2000) |
| 1999 |
|---|
| 35 | EE | Xun Liu,
Marios C. Papaefthymiou,
Eby G. Friedman:
Maximizing Performance by Retiming and Clock Skew Scheduling.
DAC 1999: 231-236 |
| 34 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Equivalent Elmore Delay for RLC Trees.
DAC 1999: 715-720 |
| 33 | EE | Yehea I. Ismail,
Eby G. Friedman:
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits.
DAC 1999: 721-724 |
| 32 | EE | Xun Liu,
Marios C. Papaefthymiou,
Eby G. Friedman:
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits.
DATE 1999: 643-649 |
| 31 | EE | Radu M. Secareanu,
Ivan S. Kourtev,
Juan Becerra,
Thomas E. Watrobski,
Christopher Morton,
William Staub,
Thomas Tellier,
Eby G. Friedman:
Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems.
Great Lakes Symposium on VLSI 1999: 314-317 |
| 30 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Inductance Effects in RLC Trees.
Great Lakes Symposium on VLSI 1999: 56-59 |
| 29 | EE | Ivan S. Kourtev,
Eby G. Friedman:
Clock skew scheduling for improved reliability via quadratic programming.
ICCAD 1999: 239-243 |
| 28 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Repeater insertion in tree structured inductive interconnect.
ICCAD 1999: 420-424 |
| 27 | EE | Radu M. Secareanu,
Eby G. Friedman,
Juan Becerra,
Scott Warner:
A universal CMOS voltage interface circuit.
ISCAS (1) 1999: 242-245 |
| 26 | EE | Kevin T. Tang,
Eby G. Friedman:
Peak noise prediction in loosely coupled interconnect [VLSI circuits].
ISCAS (1) 1999: 541-544 |
| 25 | EE | Radu M. Secareanu,
Eby G. Friedman:
A high precision CMOS current mirror/divider.
ISCAS (2) 1999: 314-317 |
| 24 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Signal waveform characterization in RLC trees.
ISCAS (6) 1999: 190-193 |
| 23 | EE | Yehea I. Ismail,
Eby G. Friedman:
Repeater insertion in RLC lines for minimum propagation delay.
ISCAS (6) 1999: 404-407 |
| 22 | EE | Kevin T. Tang,
Eby G. Friedman:
Interconnect coupling noise in CMOS VLSI circuits.
ISPD 1999: 48-53 |
| 21 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Figures of merit to characterize the importance of on-chip inductance.
IEEE Trans. VLSI Syst. 7(4): 442-449 (1999) |
| 1998 |
|---|
| 20 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Figures of Merit to Characterize the Importance of On-Chip Inductance.
DAC 1998: 560-565 |
| 19 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines.
Great Lakes Symposium on VLSI 1998: 39-44 |
| 18 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Power dissipated by CMOS gates driving lossless transmission lines.
ISLPED 1998: 139-142 |
| 1997 |
|---|
| 17 | EE | Tolga Soyata,
Eby G. Friedman,
James H. Mulligan Jr.:
Incorporating interconnect, register, and clock distribution delays into the retiming process.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 105-120 (1997) |
| 16 | EE | Eby G. Friedman:
High Performance Clock Distribution Networks.
VLSI Signal Processing 16(2-3): 113-116 (1997) |
| 15 | EE | José Luis Neves,
Eby G. Friedman:
Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations.
VLSI Signal Processing 16(2-3): 149-161 (1997) |
| 14 | EE | Kris Gaj,
Eby G. Friedman,
Marc J. Feldman:
Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits.
VLSI Signal Processing 16(2-3): 247-276 (1997) |
| 1996 |
|---|
| 13 | EE | José Luis Neves,
Eby G. Friedman:
Optimal Clock Skew Scheduling Tolerant to Process Variations.
DAC 1996: 623-628 |
| 12 | EE | José Luis Neves,
Eby G. Friedman:
Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew.
IEEE Trans. VLSI Syst. 4(2): 286-291 (1996) |
| 1995 |
|---|
| 11 | | José Luis Neves,
Eby G. Friedman:
Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks.
ISCAS 1995: 1576-1579 |
| 10 | | Tolga Soyata,
Eby G. Friedman,
James H. Mulligan Jr.:
Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay.
ISCAS 1995: 1748-1751 |
| 9 | EE | Brian S. Cherkauer,
Eby G. Friedman:
A unified design methodology for CMOS tapered buffers.
IEEE Trans. VLSI Syst. 3(1): 99-111 (1995) |
| 1994 |
|---|
| 8 | EE | Tolga Soyata,
Eby G. Friedman:
Retiming with non-zero clock skew, variable register, and interconnect delay.
ICCAD 1994: 234-241 |
| 7 | | Eby G. Friedman,
Sung-Mo Kang,
Eric A. Vittoz,
David J. Allstot,
Erik P. Harris,
Ran-Hong Yan:
Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS.
ISCAS 1994: 1-6 |
| 6 | | Brian S. Cherkauer,
Eby G. Friedman:
Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer Design.
ISCAS 1994: 111-114 |
| 5 | | José Luis Neves,
Eby G. Friedman:
Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew.
ISCAS 1994: 175-178 |
| 4 | EE | Brian S. Cherkauer,
Eby G. Friedman:
Channel width tapering of serially connected MOSFET's with emphasis on power dissipation.
IEEE Trans. VLSI Syst. 2(1): 100-114 (1994) |
| 1993 |
|---|
| 3 | | Eby G. Friedman:
Clock Distribution Design in VLSI Circuits. An Overview.
ISCAS 1993: 1475-1478 |
| 2 | | Tolga Soyata,
Eby G. Friedman,
James H. Mulligan Jr.:
Integration of Clock Skew and Register Delays into a Retiming Algorithm.
ISCAS 1993: 1483-1486 |
| 1 | | Brian S. Cherkauer,
Eby G. Friedman:
The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs.
ISCAS 1993: 2110-2113 |
