2007 |
19 | EE | Chih-Yen Lo,
Chen-Hsing Wang,
Kuo-Liang Cheng,
Jing-Reng Huang,
Chih-Wea Wang,
Shin-Moe Wang,
Cheng-Wen Wu:
STEAC: A Platform for Automatic SOC Test Integration.
IEEE Trans. VLSI Syst. 15(5): 541-545 (2007) |
18 | EE | Jen-Chieh Yeh,
Kuo-Liang Cheng,
Yung-Fa Chou,
Cheng-Wen Wu:
Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1101-1113 (2007) |
2005 |
17 | EE | Chih-Pin Su,
Chen-Hsing Wang,
Kuo-Liang Cheng,
Chih-Tsun Huang,
Cheng-Wen Wu:
Design and test of a scalable security processor.
ASP-DAC 2005: 372-375 |
2004 |
16 | EE | Kuo-Liang Cheng,
Jing-Reng Huang,
Chih-Wea Wang,
Chih-Yen Lo,
Li-Ming Denq,
Chih-Tsun Huang,
Shin-Wei Hung,
Jye-Yuan Lee:
An SOC Test Integration Platform and Its Industrial Realization.
ITC 2004: 1213-1222 |
2003 |
15 | EE | Kuo-Liang Cheng,
Chih-Wea Wang,
Jih-Nung Lee,
Yung-Fa Chou,
Chih-Tsun Huang,
Cheng-Wen Wu:
FAME: A Fault-Pattern Based Memory Failure Analysis Framework.
ICCAD 2003: 595-598 |
14 | EE | Chih-Wea Wang,
Kuo-Liang Cheng,
Jih-Nung Lee,
Yung-Fa Chou,
Chih-Tsun Huang,
Cheng-Wen Wu,
Frank Huang,
Hong-Tzer Yang:
Fault Pattern Oriented Defect Diagnosis for Memories.
ITC 2003: 29-38 |
13 | EE | Chih-Wea Wang,
Kuo-Liang Cheng,
Chih-Tsun Huang,
Cheng-Wen Wu:
Test and Diagnosis of Word-Oriented Multiport Memories.
VTS 2003: 248-253 |
2002 |
12 | EE | Chih-Wea Wang,
Jing-Reng Huang,
Yen-Fu Lin,
Kuo-Liang Cheng,
Chih-Tsun Huang,
Cheng-Wen Wu,
Youn-Long Lin:
Test Scheduling of BISTed Memory Cores for SOC.
Asian Test Symposium 2002: 356- |
11 | EE | Huan-Shan Hsu,
Jing-Reng Huang,
Kuo-Liang Cheng,
Chih-Wea Wang,
Chih-Tsun Huang,
Cheng-Wen Wu,
Youn-Long Lin:
Test Scheduling and Test Access Architecture Optimization for System-on-Chip.
Asian Test Symposium 2002: 411- |
10 | EE | Jen-Chieh Yeh,
Chi-Feng Wu,
Kuo-Liang Cheng,
Yung-Fa Chou,
Chih-Tsun Huang,
Cheng-Wen Wu:
Flash Memory Built-In Self-Test Using March-Like Algorithm.
DELTA 2002: 137-141 |
9 | EE | Kuo-Liang Cheng,
Jen-Chieh Yeh,
Chih-Wea Wang,
Chih-Tsun Huang,
Cheng-Wen Wu:
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics.
VTS 2002: 281-288 |
8 | EE | Kuo-Liang Cheng,
Ming-Fu Tsai,
Cheng-Wen Wu:
Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1328-1336 (2002) |
7 | EE | Chi-Feng Wu,
Chih-Tsun Huang,
Kuo-Liang Cheng,
Cheng-Wen Wu:
Fault simulation and test algorithm generation for random accessmemories.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 480-490 (2002) |
2001 |
6 | EE | Kuo-Liang Cheng,
Chia-Ming Hsueh,
Jing-Reng Huang,
Jen-Chieh Yeh,
Chih-Tsun Huang,
Cheng-Wen Wu:
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip.
Asian Test Symposium 2001: 91-96 |
5 | EE | Chi-Feng Wu,
Chih-Tsun Huang,
Kuo-Liang Cheng,
Chih-Wea Wang,
Cheng-Wen Wu:
Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories.
DAC 2001: 301-306 |
4 | | Jin-Fu Li,
Kuo-Liang Cheng,
Chih-Tsun Huang,
Cheng-Wen Wu:
March-based RAM diagnosis algorithms for stuck-at and coupling faults.
ITC 2001: 758-767 |
3 | EE | Kuo-Liang Cheng,
Ming-Fu Tsai,
Cheng-Wen Wu:
Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories.
VTS 2001: 225-230 |
2000 |
2 | | Chi-Feng Wu,
Chih-Tsun Huang,
Chih-Wea Wang,
Kuo-Liang Cheng,
Cheng-Wen Wu:
Error Catch and Analysis for Semiconductor Memories Using March Tests.
ICCAD 2000: 468-471 |
1 | EE | Chi-Feng Wu,
Chih-Tsun Huang,
Kuo-Liang Cheng,
Cheng-Wen Wu:
Simulation-Based Test Algorithm Generation for Random Access Memories.
VTS 2000: 291-296 |