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Mohammad Tehranipoor

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2008
40 Cristiana Bolchini, Yong-Bin Kim, Dimitris Gizopoulos, Mohammad Tehranipoor: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA IEEE Computer Society 2008
39 Mohammad Tehranipoor, Jim Plusquellic: IEEE International Workshop on Hardware-Oriented Security and Trust, HOST 2008, Anaheim, CA, USA, June 9, 2008. Proceedings IEEE Computer Society 2008
38EEJeremy Lee, Sumit Narayan, Mike Kapralos, Mohammad Tehranipoor: Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation. DATE 2008: 1172-1177
37EEXiaoxiao Wang, Hassan Salmani, Mohammad Tehranipoor, James F. Plusquellic: Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis. DFT 2008: 87-95
36EEXiaoxiao Wang, Mohammad Tehranipoor, Jim Plusquellic: Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions. HOST 2008: 15-19
35EEReza M. Rad, Jim Plusquellic, Mohammad Tehranipoor: Sensitivity Analysis to Hardware Trojans using Power Supply Transient Signals. HOST 2008: 3-7
34EEReza M. Rad, Xiaoxiao Wang, Mohammad Tehranipoor, Jim Plusquellic: Power supply signal calibration techniques for improving detection resolution to hardware Trojans. ICCAD 2008: 632-639
33EEXiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Datta: Path-RO: a novel on-chip critical path delay measurement under process variations. ICCAD 2008: 640-646
32EEJeremy Lee, Mohammad Tehranipoor: LS-TDF: Low-Switching Transition Delay Fault Pattern Generation. VTS 2008: 227-232
31EEMahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor: Test-Pattern Grading and Pattern Selection for Small-Delay Defects. VTS 2008: 233-239
30EEMehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed: Low-Transition Test Pattern Generation for BIST-Based Applications. IEEE Trans. Computers 57(3): 303-315 (2008)
29EEReza M. Rad, Mohammad Tehranipoor: SCT: A novel approach for testing and configuring nanoscale devices. JETC 4(3): (2008)
2007
28EENisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram: Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design. DAC 2007: 533-538
27EENisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram: Supply Voltage Noise Aware ATPG for Transition Delay Faults. VTS 2007: 179-186
26EEMohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar: A critical-path-aware partial gating approach for test power reduction. ACM Trans. Design Autom. Electr. Syst. 12(2): (2007)
25EEMohammad Tehranipoor, Kenneth M. Butler: Guest Editors' Introduction: IR Drop in Very Deep-Submicron Designs. IEEE Design & Test of Computers 24(3): 214-215 (2007)
24EEJeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic: Securing Designs against Scan-Based Side-Channel Attacks. IEEE Trans. Dependable Sec. Comput. 4(4): 325-336 (2007)
23EENisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler: Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 896-906 (2007)
22EEMohammad Tehranipoor, Reza M. Rad: Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based Nanofabrics. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 943-958 (2007)
21EEMohammad Tehranipoor: Guest Editorial. J. Electronic Testing 23(2-3): 115-116 (2007)
20EEReza M. Rad, Mohammad Tehranipoor: Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing. JETC 3(3): (2007)
2006
19EENisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram: Timing-based delay test for screening small delay defects. DAC 2006: 320-325
18EEReza M. Rad, Mohammad Tehranipoor: A new hybrid FPGA with nanoscale clusters and CMOS routing. DAC 2006: 727-730
17EEReza M. Rad, Mohammad Tehranipoor: A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices. DFT 2006: 107-118
16EEMohammad Tehranipoor, Reza M. Rad: Fine-grained island style architecture for molecular electronic devices. FPGA 2006: 226
15EEMohammad Tehranipoor, Reza M. Rad: Test and recovery for fine-grained nanoscale architectures. FPGA 2006: 226
14EENisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram: A novel framework for faster-than-at-speed delay test considering IR-drop effects. ICCAD 2006: 198-203
13EEKee Sup Kim, Mohammad Tehranipoor: Session Abstract. VTS 2006: 292-293
12EEReza M. Rad, Mohammad Tehranipoor: SCT: An Approach For Testing and Configuring Nanoscale Devices. VTS 2006: 370-377
11EEJeremy Lee, Mohammad Tehranipoor, Jim Plusquellic: A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks. VTS 2006: 94-99
10EEJim Plusquellic, Dhruva Acharyya, Abhishek Singh, Mohammad Tehranipoor, Chintan Patel: Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method. IEEE Design & Test of Computers 23(4): 278-293 (2006)
9EENisar Ahmed, Mohammad Tehranipoor: Improving Transition Delay Test Using a Hybrid Method. IEEE Design & Test of Computers 23(5): 402-412 (2006)
2005
8EEMohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed: Low Transition LFSR for BIST-Based Applications. Asian Test Symposium 2005: 138-143
7EEMohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar: Partial Gating Optimization for Power Reduction During Test Application. Asian Test Symposium 2005: 242-247
6EENisar Ahmed, Mohammad Tehranipoor: Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique. DFT 2005: 187-198
5EEMohammad Tehranipoor: Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure. DFT 2005: 305-313
4EEJeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic: Securing Scan Design Using Lock and Key Technique. DFT 2005: 51-62
3EENisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic: At-Speed Transition Fault Testing With Low Speed Scan Enable. VTS 2005: 42-47
2EEMehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed: Pattern Generation and Estimation for Power Supply Noise Analysis. VTS 2005: 439-444
1EEMohammad Tehranipoor, Mehrdad Nourani, Krishnendu Chakrabarty: Nine-coded compression technique for testing embedded cores in SoCs. IEEE Trans. VLSI Syst. 13(6): 719-731 (2005)

Coauthor Index

1Dhruva Acharyya [10]
2Nisar Ahmed [2] [3] [6] [8] [9] [14] [19] [23] [27] [28] [30]
3Cristiana Bolchini [40]
4Kenneth M. Butler [23] [25]
5Krishnendu Chakrabarty [1] [31]
6Ramyanshu Datta [33]
7Mohammed ElShoukry [7] [26]
8Dimitris Gizopoulos [40]
9Vinay Jayaram [14] [19] [27] [28]
10Mike Kapralos [38]
11Kee Sup Kim [13]
12Yong-Bin Kim [40]
13Jeremy Lee [4] [11] [24] [32] [38]
14Sumit Narayan [38]
15Mehrdad Nourani [1] [2] [8] [30]
16Chintan Patel [4] [10] [24]
17James F. Plusquellic (Jim Plusquellic) [3] [4] [10] [11] [24] [34] [35] [36] [37] [39]
18Reza M. Rad [12] [15] [16] [17] [18] [20] [22] [29] [34] [35]
19C. P. Ravikumar [3] [7] [23] [26]
20Hassan Salmani [37]
21Abhishek Singh [10]
22Xiaoxiao Wang [33] [34] [36] [37]
23Mahmut Yilmaz [31]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)