Chien-Nan Jimmy Liu

2009
25	EE	Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging. IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 272-284 (2009)
2008
24	EE	Mu-Shun Lee, Chin-Hsun Lin, Chien-Nan Jimmy Liu, Shih-Che Lin: Quick supply current waveform estimation at gate level using existed cell library information. ACM Great Lakes Symposium on VLSI 2008: 135-138
23	EE	Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu: Effective decap insertion in area-array SoC floorplan design. ACM Trans. Design Autom. Electr. Syst. 13(4): (2008)
22	EE	Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu: An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning. J. Inf. Sci. Eng. 24(1): 115-127 (2008)
2007
21	EE	Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu: On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design. ASP-DAC 2007: 792-797
20	EE	Chin-Lung Chuang, Wei-Hsiang Cheng, Dong-Jung Lu, Chien-Nan Jimmy Liu: Hybrid Approach to Faster Functional Verification with Full Visibility. IEEE Design & Test of Computers 24(2): 154-162 (2007)
19	EE	Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: Observability Analysis on HDL Descriptions for Effective Functional Validation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1509-1521 (2007)
18	EE	Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu: An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model. IEICE Transactions 90-A(5): 1038-1044 (2007)
17	EE	Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, Jing-Yang Jou: A Tableless Approach for High-Level Power Modeling Using Neural Networks. J. Inf. Sci. Eng. 23(1): 71-90 (2007)
2006
16	EE	Wei-Hsiang Cheng, Chin-Lung Chuang, Chien-Nan Jimmy Liu: An efficient mechanism to provide full visibility for hardware debugging. ISCAS 2006
15	EE	Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu: A Scalable Power Modeling Approach for Embedded Memory Using LIB Format. PATMOS 2006: 543-552
14	EE	Chin-Cheng Kuo, Chien-Nan Jimmy Liu: On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems. VLSI-SoC 2006: 116-121
13	EE	Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu: An Efficient Approach to Build Accurate Behavioral Models of PLL Designs. IEICE Transactions 89-A(2): 391-398 (2006)
12	EE	Wenliang Tseng, Chien-Nan Jimmy Liu, Chauchin Su: Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems. IEICE Transactions 89-C(11): 1713-1718 (2006)
2005
11	EE	Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu: An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs. ACM Great Lakes Symposium on VLSI 2005: 286-290
10	EE	Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. ASP-DAC 2005: 323-326
9	EE	Wen-Tsan Hsieh, Chih-Chieh Shiue, Chien-Nan Jimmy Liu: A novel approach for high-level power modeling of sequential circuits using recurrent neural networks. ISCAS (4) 2005: 3591-3594
8	EE	Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing Ya Jou: Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs. ISCAS (6) 2005: 5682-5685
2004
7	EE	Chin-Lung Chuang, Dong-Jung Lu, Chien-Nan Jimmy Liu: A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA. Asian Test Symposium 2004: 164-169
2003
6	EE	Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou: A Design-for-Verification Technique for Functional Pattern Reduction. IEEE Design & Test of Computers 20(2): 48-55 (2003)
2002
5	EE	Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: Effective Error Diagnosis for RTL Designs in HDLs. Asian Test Symposium 2002: 362-367
2001
4	EE	Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou: An efficient design-for-verification technique for HDLs. ASP-DAC 2001: 103-108
3	EE	Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou: Automatic Functional Vector Generation Using the Interacting FSM Model. ISQED 2001: 372-377
2000
2	EE	Chien-Nan Jimmy Liu, Jing-Yang Jou: An Automatic Controller Extractor for HDL Descriptions at the RTL. IEEE Design & Test of Computers 17(3): 72-77 (2000)
1999
1	EE	Chien-Nan Jimmy Liu, Jing-Yang Jou: An Efficient Functional Coverage Test for HDL Descriptions at RTL. ICCD 1999: 325-327

Coauthor Index

1	Hung-Ming Chen	[21] [22] [23]
2	I-Ling Chen	[4] [6]
3	Wei-Hsiang Cheng	[16] [20]
4	Yi-Fang Chiu	[15] [18]
5	Chin-Lung Chuang	[7] [16] [20]
6	Wen-Tsan Hsieh	[9] [15] [17] [18]
7	Chih-Yang Hsu	[17]
8	Tai-Ying Jiang	[5] [8] [10] [19] [25]
9	Jing Ya Jou	[8]
10	Jing-Yang Jou	[1] [2] [3] [4] [5] [6] [10] [17] [19] [25]
11	Chin-Cheng Kuo	[11] [13] [14]
12	Mu-Shun Lee	[24]
13	Chin-Hsun Lin	[24]
14	Shih-Che Lin	[24]
15	Chao-Hung Lu	[21] [22] [23]
16	Dong-Jung Lu	[7] [20]
17	Chih-Chieh Shiue	[9]
18	Chauchin Su	[12]
19	Wenliang Tseng	[12]
20	Yu-Chien Wang	[11] [13]
21	Chia-Chih Yen	[3]
22	Chi-Chia Yu	[15] [18]

Colors in the list of coauthors