| 2007 |
|---|
| 6 | EE | Shinji Odanaka:
A High-Resolution Method for Quantum Confinement Transport Simulations in MOSFETs.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 80-85 (2007) |
| 2004 |
|---|
| 5 | EE | Shinji Odanaka:
Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 837-842 (2004) |
| 1995 |
|---|
| 4 | EE | Shinji Odanaka,
Tatsuo Nogi:
Massively parallel computation using a splitting-up operator method for three-dimensional device simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(7): 824-832 (1995) |
| 1991 |
|---|
| 3 | EE | Shinji Odanaka,
Akira Hiroki,
Kikuyo Ohe,
Kaori Moriyama,
Hiroyuki Umimoto:
SMART-II: a three-dimensional CAD model for submicrometer MOSFET's.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 619-628 (1991) |
| 1989 |
|---|
| 2 | EE | Hiroyuki Umimoto,
Shinji Odanaka,
Ichiro Nakao,
Hideya Esaki:
Numerical modeling of nonplanar oxidation coupled with stress effects.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(6): 599-607 (1989) |
| 1988 |
|---|
| 1 | EE | Shinji Odanaka,
Hiroyuki Umimoto,
Mutsuko Wakabayashi,
Hideya Esaki:
SMART-P: rigorous three-dimensional process simulator on a supercomputer.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(6): 675-683 (1988) |
