| 2007 |
|---|
| 3 | EE | Rutuparna Tamhankar,
Srinivasan Murali,
Stergios Stergiou,
Antonio Pullini,
Federico Angiolini,
Luca Benini,
Giovanni De Micheli:
Timing-Error-Tolerant Network-on-Chip Design Methodology.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1297-1310 (2007) |
| 2005 |
|---|
| 2 | EE | Rutuparna Tamhankar,
Srinivasan Murali,
Giovanni De Micheli:
Performance driven reliable link design for networks on chips.
ASP-DAC 2005: 749-754 |
| 1 | EE | Davide Bertozzi,
Antoine Jalabert,
Srinivasan Murali,
Rutuparna Tamhankar,
Stergios Stergiou,
Luca Benini,
Giovanni De Micheli:
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip.
IEEE Trans. Parallel Distrib. Syst. 16(2): 113-129 (2005) |
