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Tai-Ying Jiang

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2009
6EETai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging. IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 272-284 (2009)
2007
5EETai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: Observability Analysis on HDL Descriptions for Effective Functional Validation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1509-1521 (2007)
2005
4EETai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. ASP-DAC 2005: 323-326
3EETai-Ying Jiang, Chien-Nan Jimmy Liu, Jing Ya Jou: Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs. ISCAS (6) 2005: 5682-5685
2004
2 Lily Huang, Tai-Ying Jiang, Jing-Yang Jou, Heng-Liang Huang: An efficient logic extraction algorithm using partitioning and circuit encoding. ISCAS (5) 2004: 249-252
2002
1EETai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: Effective Error Diagnosis for RTL Designs in HDLs. Asian Test Symposium 2002: 362-367

Coauthor Index

1Heng-Liang Huang [2]
2Lily Huang [2]
3Jing Ya Jou [3]
4Jing-Yang Jou [1] [2] [4] [5] [6]
5Chien-Nan Jimmy Liu [1] [3] [4] [5] [6]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)