| 2009 |
|---|
| 6 | EE | Tai-Ying Jiang,
Chien-Nan Jimmy Liu,
Jing-Yang Jou:
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 272-284 (2009) |
| 2007 |
|---|
| 5 | EE | Tai-Ying Jiang,
Chien-Nan Jimmy Liu,
Jing-Yang Jou:
Observability Analysis on HDL Descriptions for Effective Functional Validation.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1509-1521 (2007) |
| 2005 |
|---|
| 4 | EE | Tai-Ying Jiang,
Chien-Nan Jimmy Liu,
Jing-Yang Jou:
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness.
ASP-DAC 2005: 323-326 |
| 3 | EE | Tai-Ying Jiang,
Chien-Nan Jimmy Liu,
Jing Ya Jou:
Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs.
ISCAS (6) 2005: 5682-5685 |
| 2004 |
|---|
| 2 | | Lily Huang,
Tai-Ying Jiang,
Jing-Yang Jou,
Heng-Liang Huang:
An efficient logic extraction algorithm using partitioning and circuit encoding.
ISCAS (5) 2004: 249-252 |
| 2002 |
|---|
| 1 | EE | Tai-Ying Jiang,
Chien-Nan Jimmy Liu,
Jing-Yang Jou:
Effective Error Diagnosis for RTL Designs in HDLs.
Asian Test Symposium 2002: 362-367 |
