Bao Liu

2009
27	EE	Bao Liu: Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution. ISQED 2009: 430-435
26	EE	Bao Liu: Robust differential asynchronous nanoelectronic circuits. ISQED 2009: 97-102
2008
25	EE	Bao Liu: Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression. DATE 2008: 527-532
24	EE	Bao Liu: Signal Probability Based Statistical Timing Analysis. DATE 2008: 562-567
2007
23	EE	Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman: A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. ASP-DAC 2007: 24-31
22	EE	Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu: Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. ICCD 2007: 71-77
21	EE	Bao Liu: Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations. ISQED 2007: 257-262
20	EE	Bao Liu, Sheldon X.-D. Tan: Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs. IEEE Trans. VLSI Syst. 15(11): 1284-1287 (2007)
19	EE	Andrew B. Kahng, Bao Liu, Qinke Wang: Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. IEEE Trans. VLSI Syst. 15(8): 904-912 (2007)
18	EE	Andrew B. Kahng, Bao Liu, Xu Xu: Statistical Timing Analysis in the Presence of Signal-Integrity Effects. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1873-1877 (2007)
2006
17	EE	Andrew B. Kahng, Bao Liu, Xu Xu: Statistical gate delay calculation with crosstalk alignment consideration. ACM Great Lakes Symposium on VLSI 2006: 223-228
16	EE	Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan: Efficient decoupling capacitor planning via convex programming methods. ISPD 2006: 102-107
15	EE	Andrew B. Kahng, Bao Liu, Xu Xu: Constructing Current-Based Gate Models Based on Existing Timing Library. ISQED 2006: 37-42
14	EE	Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan: SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching. ISQED 2006: 638-643
13	EE	Andrew B. Kahng, Bao Liu, Xu Xu: Statistical crosstalk aggressor alignment aware interconnect delay calculation. SLIP 2006: 91-97
2005
12	EE	Andrew B. Kahng, Bao Liu, Qinke Wang: Supply Voltage Degradation Aware Analytical Placement. ICCD 2005: 437-443
11	EE	Bao Liu, Lihong Ren, Yongsheng Ding: A Novel Intelligent Controller Based on Modulation of Neuroendocrine System. ISNN (3) 2005: 119-124
2004
10	EE	Andrew B. Kahng, Bao Liu, Ion I. Mandoiu: Nontree routing for reliability and yield improvement [IC layout]. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 148-156 (2004)
2003
9	EE	Andrew B. Kahng, Bao Liu: Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization. ISVLSI 2003: 183-188
8	EE	Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky: Minimum buffered routing with bounded capacitive load for slew rate and reliability control. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 241-253 (2003)
7	EE	Christoph Albrecht, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky: On the skew-bounded minimum-buffer routing tree problem. IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 937-945 (2003)
2002
6	EE	Andrew B. Kahng, Bao Liu, Ion I. Mandoiu: Non-tree routing for reliability and yield improvement. ICCAD 2002: 260-266
5	EE	Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt: Toward better wireload models in the presence of obstacles. IEEE Trans. VLSI Syst. 10(2): 177-189 (2002)
2001
4	EE	Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt: Toward better wireload models in the presence of obstacles. ASP-DAC 2001: 527-532
3	EE	Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky: Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. ICCAD 2001: 408-
2	EE	Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia: Buffered Steiner trees for difficult instances. ISPD 2001: 4-9
1	EE	Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu: Interconnect implications of growth-based structural models for VLSI circuits. SLIP 2001: 99-106

Coauthor Index

1	Christoph Albrecht	[7]
2	Charles J. Alpert	[2] [3] [8]
3	Chung-Kuan Cheng	[1] [4] [5]
4	Yongsheng Ding	[11]
5	Milos Hrkic	[2]
6	Jiang Hu	[2] [23]
7	Andrew B. Kahng	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [12] [13] [14] [15] [16] [17] [18] [19] [22] [23]
8	Sung-Mo Kang	[22]
9	Wei Li	[22]
10	John Lillis	[2]
11	Ion I. Mandoiu	[3] [6] [7] [8] [10]
12	Stephen T. Quay	[2]
13	Lihong Ren	[11]
14	Sachin S. Sapatnekar	[2]
15	Dirk Stroobandt	[4] [5]
16	A. J. Sullivan	[2]
17	Sheldon X.-D. Tan (Xiang-Dong Tan)	[14] [16] [20]
18	Ganesh Venkataraman	[23]
19	Paul G. Villarrubia (Paul Villarrubia)	[2]
20	Qinke Wang	[12] [19]
21	Xu Xu	[13] [15] [17] [18] [23]
22	Alexander Zelikovsky	[3] [7] [8]

Colors in the list of coauthors