| |
| 2007 | ||
|---|---|---|
| 2 | EE | Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda: Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 592-605 (2007) |
| 2003 | ||
| 1 | EE | Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda: Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. ICCAD 2003: 424-432 |
| 1 | Chris J. Myers | [1] [2] |
| 2 | Tomohiro Yoneda | [1] [2] |