| 2008 |
|---|
| 8 | EE | Intaik Park,
Donghwi Lee,
Erik Chmelar,
Edward J. McCluskey:
Inconsistent Fail due to Limited Tester Timing Accuracy.
VTS 2008: 47-52 |
| 2007 |
|---|
| 7 | EE | Ahmad A. Al-Yamani,
Narendra Devta-Prasanna,
Erik Chmelar,
M. Grinchuk,
Arun Gunda:
Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 907-918 (2007) |
| 2006 |
|---|
| 6 | EE | Erik Chmelar,
Edward J. McCluskey:
Session Abstract.
VTS 2006: 156-157 |
| 2005 |
|---|
| 5 | EE | Ahmad A. Al-Yamani,
Erik Chmelar,
Mikhail Grinchuck:
Segmented Addressable Scan Architecture.
VTS 2005: 405-411 |
| 2004 |
|---|
| 4 | EE | Erik Chmelar:
Subframe multiplexing for FPGA manufacturing test configuration.
FPGA 2004: 245 |
| 3 | EE | Erik Chmelar:
Minimizing the number of test configurations for FPGAs.
ICCAD 2004: 899-902 |
| 2 | EE | Erik Chmelar,
Shahin Toutounchi:
FPGA Bridging Fault Detection and Location via Differential I{DDQ}.
VTS 2004: 109-116 |
| 2003 |
|---|
| 1 | EE | Erik Chmelar:
FPGA Interconnect Delay Fault Testing.
ITC 2003: 1239-1247 |
