| 2007 |
|---|
| 8 | EE | Rutuparna Tamhankar,
Srinivasan Murali,
Stergios Stergiou,
Antonio Pullini,
Federico Angiolini,
Luca Benini,
Giovanni De Micheli:
Timing-Error-Tolerant Network-on-Chip Design Methodology.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1297-1310 (2007) |
| 2005 |
|---|
| 7 | EE | Stergios Stergiou,
Federico Angiolini,
Salvatore Carta,
Luigi Raffo,
Davide Bertozzi,
Giovanni De Micheli:
ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips.
DATE 2005: 1188-1193 |
| 6 | EE | Davide Bertozzi,
Antoine Jalabert,
Srinivasan Murali,
Rutuparna Tamhankar,
Stergios Stergiou,
Luca Benini,
Giovanni De Micheli:
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip.
IEEE Trans. Parallel Distrib. Syst. 16(2): 113-129 (2005) |
| 5 | EE | Dimitrios Voudouris,
Stergios Stergiou,
George K. Papakonstantinou:
Minimization of Reversible Wave Cascades.
IEICE Transactions 88-A(4): 1015-1023 (2005) |
| 2004 |
|---|
| 4 | EE | Stergios Stergiou,
K. Daskalakis,
George K. Papakonstantinou:
A fast and efficient heuristic ESOP minimization algorithm.
ACM Great Lakes Symposium on VLSI 2004: 78-81 |
| 3 | EE | Stergios Stergiou,
George K. Papakonstantinou:
Exact Minimization Of Esop Expressions With Less Than Eight Product Terms.
Journal of Circuits, Systems, and Computers 13(1): 1-15 (2004) |
| 2001 |
|---|
| 2 | EE | Stavros S. Cosmadakis,
Kleoni Ioannidou,
Stergios Stergiou:
View Serializable Updates of Concurrent Index Structures.
DBPL 2001: 247-262 |
| 1 | EE | George Economakos,
Stergios Stergiou,
George K. Papakonstantinou,
Vassilios Zoukos:
A Multi-Lingual Synthesis and Verification Environment.
DSD 2001: 8-15 |
