2009 |
36 | EE | Lerong Cheng,
Jinjun Xiong,
Lei He:
Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 130-140 (2009) |
2008 |
35 | EE | Leronq Cheng,
Jinjun Xiong,
Lei He:
Non-Gaussian statistical timing analysis using second-order polynomial fitting.
ASP-DAC 2008: 298-303 |
34 | EE | Ruiming Chen,
Lizheng Zhang,
Vladimir Zolotov,
Chandu Visweswariah,
Jinjun Xiong:
Static timing: Back to our roots.
ASP-DAC 2008: 310-315 |
33 | EE | Jinjun Xiong,
Vladimir Zolotov,
Chandu Visweswariah:
Incremental Criticality and Yield Gradients.
DATE 2008: 1130-1135 |
32 | EE | Wangyang Zhang,
Wenjian Yu,
Zeyi Wang,
Zhiping Yu,
Rong Jiang,
Jinjun Xiong:
An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation.
DATE 2008: 580-585 |
31 | EE | Jinjun Xiong,
Vladimir Zolotov,
Chandu Visweswariah,
Peter A. Habitz:
Optimal Margin Computation for At-Speed Test.
DATE 2008: 622-627 |
30 | EE | Vladimir Zolotov,
Jinjun Xiong,
Hanif Fatemi,
Chandu Visweswariah:
Statistical path selection for at-speed test.
ICCAD 2008: 624-631 |
29 | EE | Howard Chen,
Scott Neely,
Jinjun Xiong,
Vladimir Zolotov,
Chandu Visweswariah:
Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power.
PATMOS 2008: 178-187 |
28 | EE | Zhen Cao,
Tong Jing,
Jinjun Xiong,
Yu Hu,
Zhe Feng,
Lei He,
Xianlong Hong:
Fashion: A Fast and Accurate Solution to Global Routing Problem.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 726-737 (2008) |
27 | EE | Yiyu Shi,
Jinjun Xiong,
Chunchen Liu,
Lei He:
Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1253-1263 (2008) |
2007 |
26 | EE | Zhen Cao,
Tong Jing,
Jinjun Xiong,
Yu Hu,
Lei He,
Xianlong Hong:
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm.
ASP-DAC 2007: 256-261 |
25 | EE | Lerong Cheng,
Jinjun Xiong,
Lei He:
Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources.
DAC 2007: 250-255 |
24 | EE | Vikram Iyengar,
Jinjun Xiong,
Subbayyan Venkatesan,
Vladimir Zolotov,
David E. Lackey,
Peter A. Habitz,
Chandu Visweswariah:
Variation-aware performance verification using at-speed structural test and statistical timing.
ICCAD 2007: 405-412 |
23 | EE | Vladimir Zolotov,
Jinjun Xiong,
S. Abbaspour,
David J. Hathaway,
Chandu Visweswariah:
Compact modeling of variational waveforms.
ICCAD 2007: 705-712 |
22 | EE | Yiyu Shi,
Jinjun Xiong,
Chunchen Liu,
Lei He:
Efficient decoupling capacitance budgeting considering operation and process variations.
ICCAD 2007: 803-810 |
21 | EE | Jinjun Xiong,
Vladimir Zolotov,
Lei He:
Robust Extraction of Spatial Correlation.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 619-631 (2007) |
20 | EE | Jinjun Xiong,
Lei He:
Probabilistic Transitive-Closure Ordering and Its Application on Variational Buffer Insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 739-742 (2007) |
19 | EE | Lei He,
Andrew B. Kahng,
King Ho Tam,
Jinjun Xiong:
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 845-857 (2007) |
18 | EE | Jinjun Xiong,
Lei He:
Full-chip multilevel routing for power and signal integrity.
Integration 40(3): 226-234 (2007) |
2006 |
17 | EE | Changbo Long,
Jinjun Xiong,
Yongpan Liu:
Techniques of Power-gating to Kill Sub-Threshold Leakage.
APCCAS 2006: 952-955 |
16 | EE | Jinjun Xiong,
Yiu-Chung Wong,
Egino Sarto,
Lei He:
Constraint driven I/O planning and placement for chip-package co-design.
ASP-DAC 2006: 207-212 |
15 | EE | Jinjun Xiong,
Vladimir Zolotov,
Natesan Venkateswaran,
Chandu Visweswariah:
Criticality computation in parameterized statistical timing.
DAC 2006: 63-68 |
14 | EE | Lerong Cheng,
Jinjun Xiong,
Lei He,
Mike Hutton:
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations.
FPL 2006: 1-6 |
13 | EE | Jinjun Xiong,
Lei He:
Fast buffer insertion considering process variations.
ISPD 2006: 128-135 |
12 | EE | Jinjun Xiong,
Vladimir Zolotov,
Lei He:
Robust extraction of spatial correlation.
ISPD 2006: 2-9 |
2005 |
11 | EE | Tong Jing,
Ling Zhang,
Jinghong Liang,
Jingyu Xu,
Xianlong Hong,
Jinjun Xiong,
Lei He:
A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem.
ASP-DAC 2005: 115-120 |
10 | EE | Jinjun Xiong,
Lei He:
Probabilistic congestion model considering shielding for crosstalk reduction.
ASP-DAC 2005: 739-742 |
9 | EE | Jinjun Xiong,
King Ho Tam,
Lei He:
Buffer Insertion Considering Process Variation.
DATE 2005: 970-975 |
8 | EE | Lei He,
Andrew B. Kahng,
King Ho Tam,
Jinjun Xiong:
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation.
ISPD 2005: 78-85 |
7 | EE | Jinjun Xiong,
Lei He:
Extended global routing with RLC crosstalk constraints.
IEEE Trans. VLSI Syst. 13(3): 319-329 (2005) |
2004 |
6 | EE | Jinjun Xiong,
Lei He:
Full-Chip Multilevel Routing for Power and Signal Integrity.
DATE 2004: 1116-1123 |
5 | | Xin Zhao,
Yici Cai,
Qiang Zhou,
Xianlong Hong,
Lei He,
Jinjun Xiong:
Shielding area optimization under the solution of interconnect crosstalk.
ISCAS (5) 2004: 297-300 |
4 | | Ling Zhang,
Tong Jing,
Xianlong Hong,
Jingyu Xu,
Jinjun Xiong,
Lei He:
Performance and RLC crosstalk driven global routing.
ISCAS (5) 2004: 65-68 |
3 | EE | Changbo Long,
Jinjun Xiong,
Lei He:
On optimal physical synthesis of sleep transistors.
ISPD 2004: 156-161 |
2 | EE | Jinjun Xiong,
Lei He:
Full-chip routing optimization with RLC crosstalk budgeting.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 366-377 (2004) |
2002 |
1 | EE | Jinjun Xiong,
Jun Chen,
James Ma,
Lei He:
Post global routing RLC crosstalk budgeting.
ICCAD 2002: 504-509 |