Kunhyuk Kang

2009
15	EE	Jing Li, Kunhyuk Kang, Kaushik Roy: Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 46-59 (2009)
2008
14	EE	Kunhyuk Kang, Saakshi Gangwal, Sang Phill Park, Kaushik Roy: NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution? ASP-DAC 2008: 726-731
2007
13	EE	Jing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy: High Performance and Low Power Electronics on Flexible Substrate. DAC 2007: 274-275
12	EE	Kunhyuk Kang, Kee-Jong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy: Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement. DAC 2007: 358-363
11	EE	Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy: Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop. DAC 2007: 934-939
10	EE	Kunhyuk Kang, Sang Phill Park, Kaushik Roy, Muhammad Ashraful Alam: Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance. ICCAD 2007: 730-734
9	EE	Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy: Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies. IEEE Trans. VLSI Syst. 15(6): 660-671 (2007)
8	EE	Kunhyuk Kang, Haldun Kufluoglu, Kaushik Roy, Muhammad Ashraful Alam: Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1770-1781 (2007)
7	EE	Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy: Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 743-751 (2007)
2006
6	EE	Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy: Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits. DATE 2006: 780-785
5	EE	Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy: Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI. ICCD 2006
4	EE	Kunhyuk Kang, Bipul C. Paul, Kaushik Roy: Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters. ACM Trans. Design Autom. Electr. Syst. 11(4): 848-879 (2006)
2005
3	EE	Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy: Statistical Timing Analysis using Levelized Covariance Propagation. DATE 2005: 764-769
2		Amit Agarwal, Kunhyuk Kang, Kaushik Roy: Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations. ICCAD 2005: 736-741
1	EE	Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy: Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations. ISLPED 2005: 14-19

Coauthor Index

1	Amit Agarwal	[1] [2] [9]
2	Muhammad Ashraful Alam	[5] [6] [7] [8] [10] [12]
3	Aditya Bansal	[13]
4	Swarup Bhunia	[1] [9]
5	James D. Gallagher	[1] [9]
6	Saakshi Gangwal	[14]
7	Ahmad E. Islam	[12]
8	Kee-Jong Kim	[11] [12]
9	Haldun Kufluoglu	[5] [6] [7] [8]
10	Jing Li	[13] [15]
11	Sang Phill Park	[10] [14]
12	Bipul Chandra Paul (Bipul C. Paul)	[3] [4] [6] [7]
13	Kaushik Roy	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]