| 2009 |
|---|
| 10 | EE | Andrew DeOrio,
Ilya Wagner,
Valeria Bertacco:
Dacota: Post-silicon validation of the memory subsystem in multi-core designs.
HPCA 2009: 405-416 |
| 2008 |
|---|
| 9 | EE | Ilya Wagner,
Valeria Bertacco:
MCjammer: Adaptive Verification for Multi-core Designs.
DATE 2008: 670-675 |
| 8 | EE | Ilya Wagner,
Valeria Bertacco:
Reversi: Post-silicon validation system for modern microprocessors.
ICCD 2008: 307-314 |
| 7 | EE | Joseph L. Greathouse,
Ilya Wagner,
David A. Ramos,
Gautam Bhatnagar,
Todd M. Austin,
Valeria Bertacco,
Seth Pettie:
Testudo: Heavyweight security analysis via statistical sampling.
MICRO 2008: 117-128 |
| 6 | EE | Ilya Wagner,
Valeria Bertacco,
Todd M. Austin:
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 380-393 (2008) |
| 2007 |
|---|
| 5 | EE | Ilya Wagner,
Valeria Bertacco:
Engineering trust with semantic guardians.
DATE 2007: 743-748 |
| 4 | EE | Ilya Wagner,
Valeria Bertacco,
Todd M. Austin:
Microprocessor Verification via Feedback-Adjusted Markov Models.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1126-1138 (2007) |
| 2006 |
|---|
| 3 | EE | Ilya Wagner,
Valeria Bertacco,
Todd M. Austin:
Depth-driven verification of simultaneous interfaces.
ASP-DAC 2006: 442-447 |
| 2 | EE | Ilya Wagner,
Valeria Bertacco,
Todd M. Austin:
Shielding against design flaws with field repairable control logic.
DAC 2006: 344-347 |
| 2005 |
|---|
| 1 | EE | Ilya Wagner,
Valeria Bertacco,
Todd M. Austin:
StressTest: an automatic approach to test generation via activity monitors.
DAC 2005: 783-788 |
