Marcello Lajolo

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20EESimone Medardoni, Marcello Lajolo, Davide Bertozzi: Variation tolerant NoC design by means of self-calibrating links. DATE 2008: 1402-1407
19EEAndré C. Nácul, Francesco Regazzoni, Marcello Lajolo: Hardware scheduling support in SMP architectures. DATE 2007: 642-647
18EEGustavo de Veciana, Marcello Lajolo, Chen He, Enrico Macii, Sachin S. Sapatnekar: In Memoriam: Margarida F. Jacome. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1549-1550 (2007)
17EESathish Chandra, Francesco Regazzoni, Marcello Lajolo: Hardware/software partitioning of operating systems: a behavioral synthesis approach. ACM Great Lakes Symposium on VLSI 2006: 324-329
16EESubhek Garg, Marcello Lajolo: C-based Design of a Flexible Wrapper for Tiled Networks On Chip. FDL 2006: 185-189
15EEAbhishek Mitra, Marcello Lajolo, Kanishka Lahiri: SOFTENIT: a methodology for boosting the software content of system-on-chip designs. ACM Great Lakes Symposium on VLSI 2005: 361-366
14EEAndré C. Nácul, Marcello Lajolo, T. Givarjis: Interface-Centric Abstraction Level for Rapid HW/SW Integration. FDL 2005: 329-341
13EEFrancesco Regazzoni, André C. Nácul, Marcello Lajolo: Automatic synthesis of the Hardware/Software Interface. FDL 2005: 401-405
12EEChen He, Marcello Lajolo, Margarida F. Jacome: A Case Study of a System Level Approach to Exploration of Queuing Management Schemes for Input Queue Packet Switches. PDP 2003: 401-408
11EEMarcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno: Cosimulation-based power estimation for system-on-chip design. IEEE Trans. VLSI Syst. 10(3): 253-266 (2002)
10EEMarcello Lajolo, Matteo Sonza Reorda, Massimo Violante: Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. VLSI Design 2001: 371-
9EEMarcello Lajolo: Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses. IEEE Trans. VLSI Syst. 9(6): 974-982 (2001)
8EEMarcello Lajolo, Luciano Lavagno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Automatic test bench generation for simulation-based validation. CODES 2000: 136-140
7EEMarcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno: Efficient Power Co-Estimation Techniques for System-on-Chip Design. DATE 2000: 27-34
6EEMarcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno: Evaluating System Dependability in a Co-Design Framework. DATE 2000: 586-590
5EEMarcello Lajolo, Luciano Lavagno, Matteo Sonza Reorda, Massimo Violante: Early Power Estimation for System-on-Chip Designs. PATMOS 2000: 108-117
4EEMarcello Lajolo, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli: Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment. ASP-DAC 1999: 347-
3EEMarcello Lajolo, Mihai Lazarescu, Alberto L. Sangiovanni-Vincentelli: A compilation-based software estimation scheme for hardware/software co-simulation. CODES 1999: 85-89
2EEMarcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli: A case study on modeling shared memory access effects during performance analysis of HW/SW systems. CODES 1998: 117-121
1EEJie Liu, Marcello Lajolo, Alberto L. Sangiovanni-Vincentelli: Software timing analysis using HW/SW cosimulation and instruction set simulator. CODES 1998: 65-69

Coauthor Index

1Davide Bertozzi [20]
2Sathish Chandra [17]
3Sujit Dey [2] [7] [11]
4Subhek Garg [16]
5T. Givarjis [14]
6Chen He [12] [18]
7Margarida F. Jacome [12]
8Kanishka Lahiri [15]
9Luciano Lavagno [2] [4] [5] [6] [7] [8] [11]
10Mihai Lazarescu [3]
11Jie Liu [1]
12Enrico Macii [18]
13Simone Medardoni [20]
14Abhishek Mitra [15]
15André C. Nácul [13] [14] [19]
16Anand Raghunathan [2] [7] [11]
17Maurizio Rebaudengo [6] [8]
18Francesco Regazzoni [13] [17] [19]
19Matteo Sonza Reorda [5] [6] [8] [10]
20Alberto L. Sangiovanni-Vincentelli [1] [2] [3] [4]
21Sachin S. Sapatnekar [18]
22Gustavo de Veciana [18]
23Massimo Violante [5] [6] [8] [10]

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Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)