2008 |
20 | EE | Simone Medardoni,
Marcello Lajolo,
Davide Bertozzi:
Variation tolerant NoC design by means of self-calibrating links.
DATE 2008: 1402-1407 |
2007 |
19 | EE | André C. Nácul,
Francesco Regazzoni,
Marcello Lajolo:
Hardware scheduling support in SMP architectures.
DATE 2007: 642-647 |
18 | EE | Gustavo de Veciana,
Marcello Lajolo,
Chen He,
Enrico Macii,
Sachin S. Sapatnekar:
In Memoriam: Margarida F. Jacome.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1549-1550 (2007) |
2006 |
17 | EE | Sathish Chandra,
Francesco Regazzoni,
Marcello Lajolo:
Hardware/software partitioning of operating systems: a behavioral synthesis approach.
ACM Great Lakes Symposium on VLSI 2006: 324-329 |
16 | EE | Subhek Garg,
Marcello Lajolo:
C-based Design of a Flexible Wrapper for Tiled Networks On Chip.
FDL 2006: 185-189 |
2005 |
15 | EE | Abhishek Mitra,
Marcello Lajolo,
Kanishka Lahiri:
SOFTENIT: a methodology for boosting the software content of system-on-chip designs.
ACM Great Lakes Symposium on VLSI 2005: 361-366 |
14 | EE | André C. Nácul,
Marcello Lajolo,
T. Givarjis:
Interface-Centric Abstraction Level for Rapid HW/SW Integration.
FDL 2005: 329-341 |
13 | EE | Francesco Regazzoni,
André C. Nácul,
Marcello Lajolo:
Automatic synthesis of the Hardware/Software Interface.
FDL 2005: 401-405 |
2003 |
12 | EE | Chen He,
Marcello Lajolo,
Margarida F. Jacome:
A Case Study of a System Level Approach to Exploration of Queuing Management Schemes for Input Queue Packet Switches.
PDP 2003: 401-408 |
2002 |
11 | EE | Marcello Lajolo,
Anand Raghunathan,
Sujit Dey,
Luciano Lavagno:
Cosimulation-based power estimation for system-on-chip design.
IEEE Trans. VLSI Syst. 10(3): 253-266 (2002) |
2001 |
10 | EE | Marcello Lajolo,
Matteo Sonza Reorda,
Massimo Violante:
Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs.
VLSI Design 2001: 371- |
9 | EE | Marcello Lajolo:
Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses.
IEEE Trans. VLSI Syst. 9(6): 974-982 (2001) |
2000 |
8 | EE | Marcello Lajolo,
Luciano Lavagno,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Automatic test bench generation for simulation-based validation.
CODES 2000: 136-140 |
7 | EE | Marcello Lajolo,
Anand Raghunathan,
Sujit Dey,
Luciano Lavagno:
Efficient Power Co-Estimation Techniques for System-on-Chip Design.
DATE 2000: 27-34 |
6 | EE | Marcello Lajolo,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante,
Luciano Lavagno:
Evaluating System Dependability in a Co-Design Framework.
DATE 2000: 586-590 |
5 | EE | Marcello Lajolo,
Luciano Lavagno,
Matteo Sonza Reorda,
Massimo Violante:
Early Power Estimation for System-on-Chip Designs.
PATMOS 2000: 108-117 |
1999 |
4 | EE | Marcello Lajolo,
Luciano Lavagno,
Alberto L. Sangiovanni-Vincentelli:
Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment.
ASP-DAC 1999: 347- |
3 | EE | Marcello Lajolo,
Mihai Lazarescu,
Alberto L. Sangiovanni-Vincentelli:
A compilation-based software estimation scheme for hardware/software co-simulation.
CODES 1999: 85-89 |
1998 |
2 | EE | Marcello Lajolo,
Anand Raghunathan,
Sujit Dey,
Luciano Lavagno,
Alberto L. Sangiovanni-Vincentelli:
A case study on modeling shared memory access effects during performance analysis of HW/SW systems.
CODES 1998: 117-121 |
1 | EE | Jie Liu,
Marcello Lajolo,
Alberto L. Sangiovanni-Vincentelli:
Software timing analysis using HW/SW cosimulation and instruction set simulator.
CODES 1998: 65-69 |