| 2008 |
|---|
| 78 | | Vijaykrishnan Narayanan,
C. P. Ravikumar,
Jörg Henkel,
Ali Keshavarzi,
Vojin G. Oklobdzija,
Barry M. Pangrle:
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008
ACM 2008 |
| 77 | EE | C. P. Ravikumar,
M. Hirech,
X. Wen:
Test Strategies for Low Power Devices.
DATE 2008: 728-733 |
| 76 | EE | Aman Kokrady,
C. P. Ravikumar,
Nitin Chandrachoodan:
Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models.
VLSI Design 2008: 169-174 |
| 75 | EE | T. S. Rajesh Kumar,
C. P. Ravikumar,
R. Govindarajan:
Memory Architecture Exploration Framework for Cache Based Embedded SOC.
VLSI Design 2008: 553-559 |
| 2007 |
|---|
| 74 | EE | T. S. Rajesh Kumar,
C. P. Ravikumar,
R. Govindarajan:
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip.
ASP-DAC 2007: 492-497 |
| 73 | EE | V. R. Devanathan,
C. P. Ravikumar,
V. Kamakoti:
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests.
DATE 2007: 534-539 |
| 72 | EE | V. R. Devanathan,
C. P. Ravikumar,
V. Kamakoti:
Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms.
VLSI Design 2007: 351-356 |
| 71 | EE | T. S. Rajesh Kumar,
C. P. Ravikumar,
R. Govindarajan:
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip.
VLSI Design 2007: 527-533 |
| 70 | EE | V. R. Devanathan,
C. P. Ravikumar,
V. Kamakoti:
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.
VTS 2007: 167-172 |
| 69 | EE | Mohammed ElShoukry,
Mohammad Tehranipoor,
C. P. Ravikumar:
A critical-path-aware partial gating approach for test power reduction.
ACM Trans. Design Autom. Electr. Syst. 12(2): (2007) |
| 68 | EE | C. P. Ravikumar,
Jari Nurmi:
Conference Reports.
IEEE Design & Test of Computers 24(2): 202-203 (2007) |
| 67 | EE | V. R. Devanathan,
C. P. Ravikumar,
V. Kamakoti:
Variation-Tolerant, Power-Safe Pattern Generation.
IEEE Design & Test of Computers 24(4): 374-384 (2007) |
| 66 | EE | Nisar Ahmed,
Mohammad Tehranipoor,
C. P. Ravikumar,
Kenneth M. Butler:
Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 896-906 (2007) |
| 65 | EE | Arasu T. Senthil,
C. P. Ravikumar,
S. K. Nandy:
Low-Power Hierarchical Scan Test for Multiple Clock Domains.
J. Low Power Electronics 3(1): 106-118 (2007) |
| 2006 |
|---|
| 64 | EE | Mitra Subhasish,
Ondrej Novák,
Hana Kubatova,
Bashir M. Al-Hashimi,
Erik Jan Marinissen,
C. P. Ravikumar:
Conference Reports.
IEEE Design & Test of Computers 23(4): 262-265 (2006) |
| 63 | EE | V. R. Devanathan,
C. P. Ravikumar,
V. Kamakoti:
On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores.
J. Low Power Electronics 2(3): 464-476 (2006) |
| 2005 |
|---|
| 62 | EE | Mohammed ElShoukry,
Mohammad Tehranipoor,
C. P. Ravikumar:
Partial Gating Optimization for Power Reduction During Test Application.
Asian Test Symposium 2005: 242-247 |
| 61 | EE | C. P. Ravikumar,
R. Dandamudi,
V. R. Devanathan,
N. Haldar,
K. Kiran,
P. S. Vijay Kumar:
A Framework for Distributed and Hierarchical Design-for-Test.
VLSI Design 2005: 497-503 |
| 60 | EE | Nisar Ahmed,
C. P. Ravikumar,
Mohammad Tehranipoor,
Jim Plusquellic:
At-Speed Transition Fault Testing With Low Speed Scan Enable.
VTS 2005: 42-47 |
| 2004 |
|---|
| 59 | EE | C. P. Ravikumar,
Graham Hetherington:
A Holistic Parallel and Hierarchical Approach towards Design-For-Test.
ITC 2004: 345-354 |
| 58 | EE | C. P. Ravikumar:
Multiprocessor Architectures for Embedded System-on-chip Applications.
VLSI Design 2004: 512-519 |
| 57 | EE | Aman Kokrady,
C. P. Ravikumar:
Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures.
VLSI Design 2004: 597- |
| 56 | EE | Mohammed Fadle Abdulla,
C. P. Ravikumar:
A self-checking signature scheme for checking backdoor security attacks in Internet.
J. High Speed Networks 13(4): 309-317 (2004) |
| 2003 |
|---|
| 55 | EE | Aman Kokrady,
C. P. Ravikumar:
Static Verification of Test Vectors for IR Drop Failure.
ICCAD 2003: 760-764 |
| 54 | EE | C. P. Ravikumar,
Nitin Kakkar,
Saurabh Chopra:
Mutual Testing based on Wavelet Transforms.
VLSI Design 2003: 347-352 |
| 2002 |
|---|
| 53 | | Mirza Mohd. Sufyan Beg,
C. P. Ravikumar:
Measuring the Quality of Web Search Results.
JCIS 2002: 324-328 |
| 52 | EE | Vineet Sahula,
C. P. Ravikumar,
D. Nagchoudhuri:
Improvement of ASIC Design Processes.
VLSI Design 2002: 105- |
| 51 | EE | S. Chakraverty,
C. P. Ravikumar,
D. Roy Choudhuri:
An Evolutionary Scheme for Cosynthesis of Real-Time Systems.
VLSI Design 2002: 251- |
| 50 | EE | Rahul Kumar,
C. P. Ravikumar:
Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment.
VLSI Design 2002: 45-50 |
| 49 | EE | C. P. Ravikumar,
Rahul Kumar:
Divide-and-Conquer IDDQ Testing for Core-Based System Chips.
VLSI Design 2002: 761-766 |
| 2001 |
|---|
| 48 | EE | Vishal Dalal,
C. P. Ravikumar:
Software Power Optimizations In An Embedded System.
VLSI Design 2001: 254- |
| 47 | EE | V. Sankara Subramanian,
C. P. Ravikumar:
Estimating Crosstalk From Vlsi Layouts.
VLSI Design 2001: 531- |
| 46 | EE | Vineet Sahula,
C. P. Ravikumar:
The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes.
VLSI Design 2001: 91-96 |
| 2000 |
|---|
| 45 | EE | Rajesh Kannah,
C. P. Ravikumar:
Functional Testing of Microprocessors with Graded Fault Coverage.
Asian Test Symposium 2000: 204- |
| 44 | EE | S. Chakraverty,
C. P. Ravikumar:
A Stochastic Framework for Co-synthesis of Real-Time Systems.
LCTES 2000: 96-113 |
| 43 | | Anil Sharma,
C. P. Ravikumar:
Efficient Implementation of ADPCM Codec.
VLSI Design 2000: 456-461 |
| 42 | EE | C. P. Ravikumar,
Gaurav Chandra,
Ashutosh Verma:
Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems.
VLSI Design 2000: 462-467 |
| 1999 |
|---|
| 41 | EE | C. P. Ravikumar,
Ashutosh Verma,
Gaurav Chandra:
A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems.
Asian Test Symposium 1999: 107-112 |
| 40 | EE | Rohit Sharma,
C. P. Ravikumar:
Design Issues in Synthesis of Reusable Cores.
Great Lakes Symposium on VLSI 1999: 144- |
| 39 | | Nishit Narang,
Girish Kumar,
C. P. Ravikumar:
Efficient Algorithms for Delay Bounded Multicast Tree Generation for Multimedia Applications.
HiPC 1999: 169-173 |
| 38 | | C. P. Ravikumar,
Meeta Sharma,
Prachi Jain:
Design of WDM Networks for Delay-Bound Multicasting.
HiPC 1999: 399-403 |
| 37 | | C. P. Ravikumar,
Manish Sharma,
R. K. Patney:
Improving the Diagnosability of Digital Circuits.
VLSI Design 1999: 629-634 |
| 36 | EE | C. P. Ravikumar,
Ajay Mittal:
Hierarchical Delay Fault Simulation.
VLSI Design 1999: 635- |
| 35 | EE | Mohammed Fadle Abdulla,
C. P. Ravikumar,
Anshul Kumar:
Built-in Self Test Based on Multiple On-Chip Signature Checking.
J. Electronic Testing 14(3): 227-244 (1999) |
| 1998 |
|---|
| 34 | EE | C. P. Ravikumar,
N. Satya Prasad:
Evaluating BIST Architectures for Low Power.
Asian Test Symposium 1998: 430-434 |
| 33 | EE | Nidhi Agrawal,
C. P. Ravikumar:
Adaptive Routing Based on Deadlock Recovery.
Euro-Par 1998: 981-988 |
| 32 | | C. P. Ravikumar,
Sumit Gupta,
Akshay Jajoo:
Synthesis of Testable RTL Designs.
VLSI Design 1998: 187-192 |
| 31 | | Mohammed Fadle Abdulla,
C. P. Ravikumar,
Anshul Kumar:
Hybrid Testing Schemes Based on Mutual and Signature Testing.
VLSI Design 1998: 293- |
| 30 | EE | Suhrid A. Wadekar,
Alice C. Parker,
C. P. Ravikumar:
Freedom: Statistical Behavioral Estimation of System Energy and Power.
VLSI Design 1998: 30-36 |
| 29 | EE | Dong-Hyun Heo,
Alice C. Parker,
C. P. Ravikumar:
An Evolutionary Approach to System Redesign.
VLSI Design 1998: 359- |
| 28 | | Mohammed Fadle Abdulla,
C. P. Ravikumar,
Anshul Kumar:
On-Chip Signature Checking for Embedded Memories.
VLSI Design 1998: 558-563 |
| 27 | EE | C. P. Ravikumar,
Rajneesh Bajpai:
Source-based delay-bounded multicasting in multimedia networks.
Computer Communications 21(2): 126-132 (1998) |
| 26 | EE | Mohammed Fadle Abdulla,
C. P. Ravikumar,
Anshul Kumar:
Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems.
J. Electronic Testing 12(3): 199-216 (1998) |
| 1997 |
|---|
| 25 | EE | Mohammed Fadle Abdulla,
C. P. Ravikumar,
Anshul Kumar:
A scheme for multiple on-chip signature checking for embedded SRAMs.
ED&TC 1997: 625 |
| 24 | EE | Nidhi Agrawal,
C. P. Ravikumar:
An Euler Path Based Technique for Deadlock-free Multicasting.
ICPP 1997: 378-384 |
| 23 | EE | C. P. Ravikumar,
R. Aggarwal,
C. Sharma:
A Graph-Theoretic Approach for Register File Based Synthesis.
VLSI Design 1997: 118-123 |
| 22 | EE | Mohammed Fadle Abdulla,
C. P. Ravikumar,
Anshul Kumar:
Efficient Implementation of Multiple On-Chip Signature Checking.
VLSI Design 1997: 297-302 |
| 21 | EE | C. P. Ravikumar,
Vikas Jain,
Anurag Dod:
Faster Fault Simulation Through Distributed Computing.
VLSI Design 1997: 482-487 |
| 20 | EE | Dong-Hyun Heo,
Alice C. Parker,
C. P. Ravikumar:
Rapid Synthesis of Multi-Chip Systems.
VLSI Design 1997: 62-68 |
| 19 | EE | C. P. Ravikumar,
Tarun Rai,
Varun Verma:
Kautz graphs as attractive logical topologies in multihop lightwave networks.
Computer Communications 20(14): 1259-1270 (1997) |
| 18 | EE | C. P. Ravikumar,
Nitin Agrawal,
Parul Agarwal:
Hierarchical Delay Test Generation.
J. Electronic Testing 10(3): 231-244 (1997) |
| 1996 |
|---|
| 17 | EE | Nidhi Agrawal,
Parul Agarwal,
C. P. Ravikumar:
Efficient Delay Test Generation for Modular Circuits.
Great Lakes Symposium on VLSI 1996: 220- |
| 16 | EE | C. P. Ravikumar,
Rajamani Rajarajan:
Genetic Algorithms for Scan Path Design.
VLSI Design 1996: 118-121 |
| 15 | | C. P. Ravikumar,
V. Saxena:
Synthesis of Testable Pipelined Datapaths Using Genetic Search.
VLSI Design 1996: 205-210 |
| 14 | EE | C. P. Ravikumar,
Mukul R. Prasad,
Lavmeet S. Hora:
Estimation of Power from Module-level Netlists.
VLSI Design 1996: 324-325 |
| 13 | EE | Mohammed Fadle Abdulla,
C. P. Ravikumar,
Anshul Kumar:
A Novel BIST Architecture With Built-in Self Check.
VLSI Design 1996: 57-60 |
| 12 | EE | C. P. Ravikumar,
R. Aggarwal:
Parallel search-and-learn techniques and graph coloring.
Knowl.-Based Syst. 9(1): 3-13 (1996) |
| 1995 |
|---|
| 11 | EE | C. P. Ravikumar,
Gurjeet S. Saund,
Nidhi Agrawal:
A STAFAN-like functional testability measure for register-level circuits.
Asian Test Symposium 1995: 192-198 |
| 10 | EE | C. P. Ravikumar,
Hemant Joshi:
HISCOAP: a hierarchical testability analysis tool.
VLSI Design 1995: 272-277 |
| 1994 |
|---|
| 9 | | C. P. Ravikumar,
H. Rasheed:
Simulated Annealing for Target-Oriented Scan.
VLSI Design 1994: 107-112 |
| 8 | EE | C. P. Ravikumar:
Parallel search-and-learn technique for solving large scale travelling-salesperson problems.
Knowl.-Based Syst. 7(3): 169-176 (1994) |
| 1993 |
|---|
| 7 | | C. P. Ravikumar,
A. Kuchlous,
G. Manimaran:
Incomplete Star Graph: An Economical Fault-tolerant Interconnection Network.
ICPP 1993: 83-90 |
| 6 | | C. P. Ravikumar:
A Parallel Search-and-Learn Technique for Solving Large Scale TSP.
ICTAI 1993: 381-388 |
| 5 | EE | C. P. Ravikumar:
Solving VLSI physical design problems on a vector machine.
Computer-Aided Design 25(1): 49-57 (1993) |
| 1992 |
|---|
| 4 | EE | C. P. Ravikumar:
Interval partition with bounded overlap.
Computer-Aided Design 24(8): 405-410 (1992) |
| 1990 |
|---|
| 3 | | C. P. Ravikumar,
Lalit M. Patnaik:
Performance improvement of simulated annealing algorithms.
Comput. Syst. Sci. Eng. 5(2): 111-115 (1990) |
| 1989 |
|---|
| 2 | | C. P. Ravikumar,
Sarma Sastry:
Parallel Placement on Hypercube Architecture.
ICPP (3) 1989: 97-101 |
| 1987 |
|---|
| 1 | | C. P. Ravikumar,
Lalit M. Patnaik:
An Architecture for CSP and Its Simulation.
ICPP 1987: 874-881 |
