| 2007 |
|---|
| 11 | EE | Bernard N. Sheehan,
Yousef Saad:
Higher Order Orthogonal Iteration of Tensors (HOOI) and its Relation to PCA and GLRAM.
SDM 2007 |
| 10 | EE | Bernard N. Sheehan:
Realizable Reduction of RC Networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1393-1407 (2007) |
| 2003 |
|---|
| 9 | EE | Bernard N. Sheehan:
Branch Merge Reduction of RLCM Networks.
ICCAD 2003: 658-664 |
| 2002 |
|---|
| 8 | EE | Bernard N. Sheehan:
Osculating Thevenin model for predicting delay and slew of capacitively characterized cells.
DAC 2002: 866-869 |
| 7 | EE | Bernard N. Sheehan:
Library Compatible Ceff for Gate-Level Timing.
DATE 2002: 826-831 |
| 2000 |
|---|
| 6 | EE | Bernard N. Sheehan:
Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments.
DAC 2000: 532-535 |
| 5 | EE | Bernard N. Sheehan:
Predicting Coupled Noise in RC Circuits.
DATE 2000: 517- |
| 1999 |
|---|
| 4 | EE | Bernard N. Sheehan:
ENOR: Model Order Reduction of RLC Circuits Using Nodal Equations for Efficient Factorization.
DAC 1999: 17-21 |
| 3 | EE | Bernard N. Sheehan:
Projective Convolution: RLC Model-Order Reduction Using the Impulse Response.
DATE 1999: 669- |
| 2 | EE | Bernard N. Sheehan:
TICER: realizable reduction of extracted RC circuits.
ICCAD 1999: 200-203 |
| 1996 |
|---|
| 1 | EE | Bernard N. Sheehan:
An AWE Technique for Fast Printed Circuit Board Delays.
DAC 1996: 539-543 |
