| 2009 |
|---|
| 81 | EE | Jason Luu,
Ian Kuon,
Peter Jamieson,
Ted Campbell,
Andy Ye,
Wei Mark Fang,
Jonathan Rose:
VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling.
FPGA 2009: 133-142 |
| 80 | EE | Peter Yiannacouras,
J. Gregory Steffan,
Jonathan Rose:
Soft vector processors vs FPGA custom hardware: measuring and reducing the gap.
FPGA 2009: 277 |
| 2008 |
|---|
| 79 | EE | Peter Yiannacouras,
J. Gregory Steffan,
Jonathan Rose:
VESPA: portable, scalable, and flexible FPGA-based vector processors.
CASES 2008: 61-70 |
| 78 | EE | Ian Kuon,
Jonathan Rose:
Automated transistor sizing for FPGA architecture exploration.
DAC 2008: 792-795 |
| 77 | EE | Wei Mark Fang,
Jonathan Rose:
Modeling routing demand for early-stage FPGA architecture development.
FPGA 2008: 139-148 |
| 76 | EE | Ian Kuon,
Jonathan Rose:
Area and delay trade-offs in the circuit and architecture design of FPGAs.
FPGA 2008: 149-158 |
| 2007 |
|---|
| 75 | EE | Ian Kuon,
Russell Tessier,
Jonathan Rose:
FPGA Architecture: Survey and Challenges.
Foundations and Trends in Electronic Design Automation 2(2): 135-253 (2007) |
| 74 | EE | Ian Kuon,
Jonathan Rose:
Measuring the Gap Between FPGAs and ASICs.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 203-215 (2007) |
| 73 | EE | Peter Yiannacouras,
J. Gregory Steffan,
Jonathan Rose:
Exploration and Customization of FPGA-Based Soft Processors.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 266-277 (2007) |
| 2006 |
|---|
| 72 | EE | Peter Yiannacouras,
J. Gregory Steffan,
Jonathan Rose:
Application-specific customization of soft processor microarchitecture.
FPGA 2006: 201-210 |
| 71 | EE | Ian Kuon,
Jonathan Rose:
Measuring the gap between FPGAs and ASICs.
FPGA 2006: 21-30 |
| 70 | EE | Andy Ye,
Jonathan Rose:
Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits.
IEEE Trans. VLSI Syst. 14(5): 462-473 (2006) |
| 69 | EE | Ahmad Darabiha,
W. James MacLean,
Jonathan Rose:
Reconfigurable hardware implementation of a phase-correlation stereoalgorithm.
Mach. Vis. Appl. 17(2): 116-132 (2006) |
| 2005 |
|---|
| 68 | EE | Peter Yiannacouras,
Jonathan Rose,
J. Gregory Steffan:
The microarchitecture of FPGA-based soft processors.
CASES 2005: 202-212 |
| 67 | EE | David M. Lewis,
Elias Ahmed,
Gregg Baeckler,
Vaughn Betz,
Mark Bourgeault,
David Cashman,
David R. Galloway,
Mike Hutton,
Christopher Lane,
Andy Lee,
Paul Leventis,
Sandy Marquardt,
Cameron McClintock,
Ketan Padalia,
Bruce Pedersen,
Giles Powell,
Boris Ratchev,
Srinivas Reddy,
Jay Schleicher,
Kevin Stevens,
Richard Yuan,
Richard Cliff,
Jonathan Rose:
The Stratix II logic and routing architecture.
FPGA 2005: 14-20 |
| 66 | EE | Ian Kuon,
Aaron Egier,
Jonathan Rose:
Design, layout and verification of an FPGA using automated tools.
FPGA 2005: 215-226 |
| 65 | EE | Andy Gean Ye,
Jonathan Rose:
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits.
FPGA 2005: 3-13 |
| 64 | | Andy Gean Ye,
Jonathan Rose:
Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks.
FPL 2005: 159-166 |
| 63 | | Peter Jamieson,
Jonathan Rose:
A Verilog RTL Synthesis Tool for Heterogeneous FPGAs.
FPL 2005: 305-310 |
| 62 | | Joshua Fender,
Jonathan Rose,
David R. Galloway:
The Transmogrifier-4: An FPGA-Based Hardware Development System with Multi-Gigabyte Memory Capacity and High Host and Memory Bandwidth.
FPT 2005: 301-302 |
| 2004 |
|---|
| 61 | EE | Ian Kuon,
Aaron Egier,
Jonathan Rose:
Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs.
FPGA 2004: 249 |
| 60 | EE | Tomasz S. Czajkowski,
Jonathan Rose:
A synthesis oriented omniscient manual editor.
FPGA 2004: 89-98 |
| 59 | EE | Anish Alex,
Jonathan Rose,
Ruth Isserlin-Weinberger,
Christopher W. V. Hogue:
Hardware Accelerated Novel Protein Identification.
FPL 2004: 13-22 |
| 58 | EE | Jonathan Rose:
Hard vs. Soft: The Central Question of Pre-Fabricated Silicon.
ISMVL 2004: 2-5 |
| 57 | | Elias Ahmed,
Jonathan Rose:
The effect of LUT and cluster size on deep-submicron FPGA performance and density.
IEEE Trans. VLSI Syst. 12(3): 288-298 (2004) |
| 56 | EE | Paul D. Kundarewich,
Jonathan Rose:
Synthetic circuit generation using clustering and iteration.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 869-887 (2004) |
| 2003 |
|---|
| 55 | EE | Ahmad Darabiha,
Jonathan Rose,
W. James MacLean:
Video-Rate Stereo Depth Measurement on Programmable Hardware.
CVPR (1) 2003: 203-210 |
| 54 | EE | David M. Lewis,
Vaughn Betz,
David Jefferson,
Andy Lee,
Christopher Lane,
Paul Leventis,
Sandy Marquardt,
Cameron McClintock,
Bruce Pedersen,
Giles Powell,
Srinivas Reddy,
Chris Wysocki,
Richard Cliff,
Jonathan Rose:
The StratixTM routing and logic architecture.
FPGA 2003: 12-20 |
| 53 | EE | Ketan Padalia,
Ryan Fung,
Mark Bourgeault,
Aaron Egier,
Jonathan Rose:
Automatic transistor and physical design of FPGA tiles from an architectural specification.
FPGA 2003: 164-172 |
| 52 | EE | Paul D. Kundarewich,
Jonathan Rose:
Synthetic circuit generation using clustering and iteration.
FPGA 2003: 245 |
| 2002 |
|---|
| 51 | EE | William Chow,
Jonathan Rose:
EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits.
FPGA 2002: 85-94 |
| 50 | EE | Michael D. Hutton,
Jonathan Rose,
Derek G. Corneil:
Automatic generation of synthetic sequential benchmark circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(8): 928-940 (2002) |
| 2001 |
|---|
| 49 | EE | Rob A. Rutenbar,
Max Baron,
Thomas Daniel,
Rajeev Jayaraman,
Zvi Or-Bach,
Jonathan Rose,
Carl Sechen:
Panel: (When) Will FPGAs Kill ASICs?
DAC 2001: 321-322 |
| 48 | EE | Mike Sheng,
Jonathan Rose:
Mixing buffers and pass transistors in FPGA routing architectures.
FPGA 2001: 75-84 |
| 47 | EE | Steven J. E. Wilton,
Jonathan Rose,
Zvonko G. Vranesic:
Structural analysis and generation of synthetic digital circuits with memory.
IEEE Trans. VLSI Syst. 9(1): 223-226 (2001) |
| 2000 |
|---|
| 46 | EE | Vaughn Betz,
Jonathan Rose:
Automatic generation of FPGA routing architectures from high-level descriptions.
FPGA 2000: 175-184 |
| 45 | EE | Alexander Marquardt,
Vaughn Betz,
Jonathan Rose:
Timing-driven placement for FPGAs.
FPGA 2000: 203-213 |
| 44 | EE | Rob McCready,
Jonathan Rose:
Real-time, frame-rate face detection on a configurable hardware system (poster abstract).
FPGA 2000: 221 |
| 43 | EE | Elias Ahmed,
Jonathan Rose:
The effect of LUT and cluster size on deep-submicron FPGA performance and density.
FPGA 2000: 3-12 |
| 42 | EE | Mohammed A. S. Khalid,
Jonathan Rose:
A novel and efficient routing architecture for multi-FPGA systems.
IEEE Trans. VLSI Syst. 8(1): 30-39 (2000) |
| 41 | EE | Alexander Marquardt,
Vaughn Betz,
Jonathan Rose:
Speed and area tradeoffs in cluster-based FPGA architectures.
IEEE Trans. VLSI Syst. 8(1): 84-93 (2000) |
| 1999 |
|---|
| 40 | EE | Yaska Sankar,
Jonathan Rose:
Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs.
FPGA 1999: 157-166 |
| 39 | EE | Alexander Marquardt,
Vaughn Betz,
Jonathan Rose:
Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density.
FPGA 1999: 37-46 |
| 38 | EE | Vaughn Betz,
Jonathan Rose:
FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density.
FPGA 1999: 59-68 |
| 37 | | Mohammed A. S. Khalid,
Jonathan Rose:
Hardwired-Clusters Partial-Crossbar: A Hierarchical Routing Architecture for Multi-FPGA Systems.
IPPS/SPDP Workshops 1999: 597-605 |
| 36 | EE | Michael D. Hutton,
Jonathan Rose:
Equivalence classes of clone circuits for physical-design benchmarking.
ISCAS (6) 1999: 428-431 |
| 35 | EE | Michael D. Hutton,
Jonathan Rose:
Applications of clone circuits to issues in physical-design.
ISCAS (6) 1999: 448-451 |
| 34 | EE | Steven J. E. Wilton,
Jonathan Rose,
Zvonko G. Vranesic:
The memory/logic interface in FPGAs with large embedded memory arrays.
IEEE Trans. VLSI Syst. 7(1): 80-91 (1999) |
| 1998 |
|---|
| 33 | EE | Jonathan Rose,
Sinan Kaptanoglu,
Clive McCarthy,
Rob Smith,
Sandip Vij,
Steve Taylor:
Constraints from Hell: How to Tell Makes a Good FPGA (Panel).
FPGA 1998: 117-119 |
| 32 | EE | Jordan S. Swartz,
Vaughn Betz,
Jonathan Rose:
A Fast Routability-Driven Router for FPGAs.
FPGA 1998: 140-149 |
| 31 | EE | Mohammed A. S. Khalid,
Jonathan Rose:
A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems.
FPGA 1998: 45-54 |
| 30 | EE | Vaughn Betz,
Jonathan Rose:
How Much Logic Should Go in an FPGA Logic Block?
IEEE Design & Test of Computers 15(1): 10-15 (1998) |
| 29 | EE | David M. Lewis,
David R. Galloway,
Marcus van Ierssel,
Jonathan Rose,
Paul Chow:
The Transmogrifier-2: a 1 million gate rapid-prototyping system.
IEEE Trans. VLSI Syst. 6(2): 188-198 (1998) |
| 28 | EE | Vaughn Betz,
Jonathan Rose:
Effect of the prefabricated routing track distribution on FPGA area-efficiency.
IEEE Trans. VLSI Syst. 6(3): 445-456 (1998) |
| 27 | EE | Michael D. Hutton,
Jonathan Rose,
Jerry P. Grossman,
Derek G. Corneil:
Characterization and parameterized generation of synthetic combinational benchmark circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 985-996 (1998) |
| 1997 |
|---|
| 26 | EE | Steven J. E. Wilton,
Jonathan Rose,
Zvonko G. Vranesic:
Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays.
FPGA 1997: 10-16 |
| 25 | EE | Jonathan Rose,
Dwight D. Hill:
Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond.
FPGA 1997: 129-132 |
| 24 | EE | Michael D. Hutton,
Jonathan Rose,
Derek G. Corneil:
Generation of Synthetic Sequential Benchmark Circuits.
FPGA 1997: 149-155 |
| 23 | EE | David M. Lewis,
David R. Galloway,
Marcus van Ierssel,
Jonathan Rose,
Paul Chow:
The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System.
FPGA 1997: 53-61 |
| 22 | | Vaughn Betz,
Jonathan Rose:
VPR: A new packing, placement and routing tool for FPGA research.
FPL 1997: 213-222 |
| 1996 |
|---|
| 21 | EE | Michael D. Hutton,
Jerry P. Grossman,
Jonathan Rose,
Derek G. Corneil:
Characterization and Parameterized Random Generation of Digital Circuits.
DAC 1996: 94-99 |
| 20 | EE | Vaughn Betz,
Jonathan Rose:
Directional bias and non-uniformity in FPGA global routing architectures.
ICCAD 1996: 652-659 |
| 19 | EE | Stephen Dean Brown,
Jonathan Rose:
FPGA and CPLD Architectures: A Tutorial.
IEEE Design & Test of Computers 13(2): 42-57 (1996) |
| 1995 |
|---|
| 18 | EE | Vaughn Betz,
Jonathan Rose:
Using Architectural ``Families'' to Increase FPGA Speed and Density.
FPGA 1995: 10-16 |
| 17 | EE | Steven J. E. Wilton,
Jonathan Rose,
Zvonko G. Vranesic:
Architecture of Centralized Field-Configurable Memory.
FPGA 1995: 97-103 |
| 1994 |
|---|
| 16 | EE | David Karchmer,
Jonathan Rose:
Definition and solution of the memory packing problem for field-programmable systems.
ICCAD 1994: 20-26 |
| 1993 |
|---|
| 15 | EE | Jonathan Rose:
Logic Emulation: A Niche or a Future Standard for Design Verification? (Panel Abstract).
DAC 1993: 164 |
| 14 | EE | Stephen Dean Brown,
Jonathan Rose,
Zvonko G. Vranesic:
A stochastic model to predict the routability of field-programmable gate arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1827-1838 (1993) |
| 1992 |
|---|
| 13 | EE | Kevin Chung,
Jonathan Rose:
TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections.
DAC 1992: 361-367 |
| 12 | | Benjamin Tseng,
Jonathan Rose,
Stephen Dean Brown:
Improving FPGA Routing Architectures Using Architecture and CAD Interactions.
ICCD 1992: 99-104 |
| 11 | EE | Stephen Dean Brown,
Jonathan Rose,
Zvonko G. Vranesic:
A detailed router for field-programmable gate arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 620-628 (1992) |
| 1991 |
|---|
| 10 | EE | Robert J. Francis,
Jonathan Rose,
Zvonko G. Vranesic:
Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs.
DAC 1991: 227-233 |
| 9 | | Jonathan Rose:
Will the Field-Programmable Gata Array Replace the Mask-Programmable Gate Array? (Panel Abstract).
DAC 1991: 779 |
| 8 | | Robert J. Francis,
Jonathan Rose,
Zvonko G. Vranesic:
Technology Mapping on Lookup Table-Based FPGAs for Performance.
ICCAD 1991: 568-571 |
| 1990 |
|---|
| 7 | EE | Robert J. Francis,
Jonathan Rose,
Kevin Chung:
Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays.
DAC 1990: 613-619 |
| 6 | | Stephen Dean Brown,
Jonathan Rose,
Zvonko G. Vranesic:
A Detailed Router for Field-Programmable Gate Arrays.
ICCAD 1990: 382-385 |
| 5 | EE | Jonathan Rose:
Parallel global routing for standard cells.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(10): 1085-1095 (1990) |
| 4 | EE | Jonathan Rose,
Wolfgang Klebsch,
Jürgen Wolf:
Temperature measurement and equilibrium dynamics of simulated annealing placements.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(3): 253-259 (1990) |
| 1988 |
|---|
| 3 | EE | Jonathan Rose:
LocusRoute: A Parallel Global Router for Standard Cells.
DAC 1988: 189-195 |
| 2 | | Jonathan Rose:
The Parallel Decomposition and Implementation of an Integrated Circuit Global Router.
PPOPP/PPEALS 1988: 138-145 |
| 1 | EE | Jonathan Rose,
W. Martin Snelgrove,
Zvonko G. Vranesic:
Parallel standard cell placement algorithms with quality equivalent to simulated annealing.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(3): 387-396 (1988) |
