| 2007 |
|---|
| 7 | EE | Murari Mani,
Anirudh Devgan,
Michael Orshansky,
Yaping Zhan:
A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1790-1802 (2007) |
| 2006 |
|---|
| 6 | EE | Murari Mani,
Mahesh Sharma,
Michael Orshansky:
Application of fast SOCP based statistical sizing in the microprocessor design flow.
ACM Great Lakes Symposium on VLSI 2006: 372-375 |
| 5 | EE | Ashish Kumar Singh,
Murari Mani,
Ruchir Puri,
Michael Orshansky:
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty.
DAC 2006: 522-527 |
| 4 | EE | Murari Mani,
Ashish Kumar Singh,
Michael Orshansky:
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization.
ICCAD 2006: 19-26 |
| 2005 |
|---|
| 3 | EE | Murari Mani,
Anirudh Devgan,
Michael Orshansky:
An efficient algorithm for statistical minimization of total power under timing yield constraints.
DAC 2005: 309-314 |
| 2 | | Ashish Kumar Singh,
Murari Mani,
Michael Orshansky:
Statistical technology mapping for parametric yield.
ICCAD 2005: 511-518 |
| 2004 |
|---|
| 1 | EE | Murari Mani,
Michael Orshansky:
A New Statistical Optimization Algorithm for Gate Sizing.
ICCD 2004: 272-277 |
