2008 | ||
---|---|---|
61 | EE | Aijiao Cui, Chip-Hong Chang: Intellectual property authentication by watermarking scan chain in design-for-testability flow. ISCAS 2008: 2645-2648 |
60 | EE | Ravi Kumar Satzoda, Ramya Muralidharan, Chip-Hong Chang: Programmable LSB-first and MSB-first modular multipliers for ECC in GF(2m). ISCAS 2008: 808-811 |
59 | EE | Aijiao Cui, Chip-Hong Chang, Sofiène Tahar: IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1565-1570 (2008) |
2007 | ||
58 | EE | Aijiao Cui, Chip-Hong Chang: Watermarking for IP Protection through Template Substitution at Logic Synthesis Level. ISCAS 2007: 3687-3690 |
57 | EE | Fei Xu, Chip-Hong Chang, Ching-Chuen Jong: Hamming weight pyramid - A new insight into canonical signed digit representation and its applications. Computers & Electrical Engineering 33(3): 195-207 (2007) |
56 | EE | Fei Xu, Chip-Hong Chang, Ching-Chuen Jong: Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common Subexpressions. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1898-1907 (2007) |
55 | EE | Yu Shao, Chip-Hong Chang: A Generalized Time-Frequency Subtraction Method for Robust Speech Enhancement Based on Wavelet Filter Banks Modeling of Human Auditory System. IEEE Transactions on Systems, Man, and Cybernetics, Part B 37(4): 877-889 (2007) |
2006 | ||
54 | EE | Aijiao Cui, Chip-Hong Chang: Kernel Extraction for Watermarking Combinational Logic Networks. APCCAS 2006: 1023-1026 |
53 | EE | Shibu Menon, Chip-Hong Chang: A Reconfigurable Multi-Modulus Modulo Multiplier. APCCAS 2006: 1168-1171 |
52 | EE | A. Prasad Vinod, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla: Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis. APCCAS 2006: 1547-1550 |
51 | EE | A. Prasad Vinod, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla: Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - Algorithm. APCCAS 2006: 1551-1554 |
50 | EE | Uwe Meyer-Bäse, Jiajia Chen, Chip-Hong Chang, Andrew G. Dempster: A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters. APCCAS 2006: 1555-1558 |
49 | EE | Jiajia Chen, Chip-Hong Chang, A. Prasad Vinod: Design of High-speed, Low-power FIR Filters with Fine-grained Cost Metrics. APCCAS 2006: 756-759 |
48 | EE | Yu Shao, Chip-Hong Chang: A Kalman filter based on wavelet filter-bank and psychoacoustic modeling for speech enhancement. ISCAS 2006 |
47 | EE | Ravi Kumar Satzoda, Chip-Hong Chang: A fast kernel for unifying GF(p) and GF(2m) Montgomery multiplications in a scalable pipelined architecture. ISCAS 2006 |
46 | EE | Yu Shao, Chip-Hong Chang: A generalized perceptual time-frequency subtraction method for speech enhancement. ISCAS 2006 |
45 | EE | Yajuan He, Chip-Hong Chang: A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier. ISCAS 2006 |
44 | EE | Fei Xu, Chip-Hong Chang, Ching-Chuen Jong: A new integrated approach to the design of low-complexity FIR filters. ISCAS 2006 |
43 | EE | Yu Shao, Chip-Hong Chang: A novel hybrid neuro-wavelet system for robust speech recognition. ISCAS 2006 |
42 | EE | A. Prasad Vinod, Ankita Singla, Chip-Hong Chang: Improved differential coefficients-based low power FIR filters. Part I. Fundamentals. ISCAS 2006 |
41 | EE | Chip-Hong Chang, Jiajia Chen, A. Prasad Vinod: Maximum likelihood disjunctive decomposition to reduced multirooted DAG for FIR filter design. ISCAS 2006 |
40 | EE | Aijiao Cui, Chip-Hong Chang: Stego-signature at logic synthesis level for digital design IP protection. ISCAS 2006 |
2005 | ||
39 | Thambipillai Srikanthan, Jingling Xue, Chip-Hong Chang: Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings Springer 2005 | |
38 | EE | Ravi Kumar Satzoda, Chip-Hong Chang: VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers. Asia-Pacific Computer Systems Architecture Conference 2005: 693-706 |
37 | EE | Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan: A new formulation of fast diminished-one multioperand modulo 2/sup n/+1 adder. ISCAS (1) 2005: 656-659 |
36 | EE | Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang: A new design method to modulo 2/sup n/-1 squaring. ISCAS (1) 2005: 664-667 |
35 | EE | Yajuan He, Chip-Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy: A novel covalent redundant binary Booth encoder. ISCAS (1) 2005: 69-72 |
34 | EE | Chip-Hong Chang, Ravi Kumar Satzoda, Swaminathan Sekar: A novel multiplexer based truncated array multiplier. ISCAS (1) 2005: 85-88 |
33 | EE | Chip-Hong Chang, Shibu Menon, Bin Cao, Thambipillai Srikanthan: A configurable dual moduli multi-operand modulo adder. ISCAS (2) 2005: 1630-1633 |
32 | EE | Fei Xu, Chip-Hong Chang, Ching-Chuen Jong: I/sup 2/CRA: contention resolution algorithm for intra- and inter-coefficient common subexpression elimination. ISCAS (2) 2005: 1823-1826 |
31 | EE | Yu Shao, Chip-Hong Chang: A versatile speech enhancement system based on perceptual wavelet denoising. ISCAS (2) 2005: 864-867 |
30 | EE | Yu Shao, Chip-Hong Chang: Wavelet transform to hybrid support vector machine and hidden Markov model for speech recognition. ISCAS (4) 2005: 3833-3836 |
29 | EE | Yajuan He, Chip-Hong Chang, Jiangmin Gu: An area efficient 64-bit square root carry-select adder for low power applications. ISCAS (4) 2005: 4082-4085 |
28 | EE | Chip-Hong Chang, Zhi Ye, Mingyan Zhang: Fuzzy-ART based adaptive digital watermarking scheme. IEEE Trans. Circuits Syst. Video Techn. 15(1): 65-81 (2005) |
27 | EE | Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang: A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits. IEEE Trans. VLSI Syst. 13(6): 686-695 (2005) |
26 | EE | Pengfei Xu, Chip-Hong Chang, Andrew P. Paplinski: Self-organizing topological tree for online vector quantization and data clustering. IEEE Transactions on Systems, Man, and Cybernetics, Part B 35(3): 515-526 (2005) |
25 | EE | Zhi-Hui Kong, Kiat Seng Yeo, Chip-Hong Chang: An Ultra Low-power Current-mode Sense Amplifier for Sram Applications. Journal of Circuits, Systems, and Computers 14(5): 939-952 (2005) |
2004 | ||
24 | EE | Zhi Ye, Chip-Hong Chang: Local Search Method for FIR Filter Coefficients Synthesis. DELTA 2004: 255-260 |
23 | EE | Xiaoyun Deng, Chip-Hong Chang, Erwin Brandle: A New Method for Eye Extraction from Facial Image. DELTA 2004: 29-34 |
22 | EE | Zhi Ye, Ravi Kumar Satzoda, Udit Sharma, Naveen Nazimudeen, Chip-Hong Chang: Performance Evaluation of Direct Form FIR Filter with Merged Arithmetic Architecture. DELTA 2004: 407-409 |
21 | Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang: Design of residue-to-binary converter for a new 5-moduli superset residue number system. ISCAS (2) 2004: 841-844 | |
20 | EE | Fei Xu, Chip-Hong Chang, Ching-Chuen Jong: A new contention resolution algorithm for the design of minimal logic depth multiplierless filters. ISCAS (3) 2004: 481-484 |
19 | Fei Xu, Chip-Hong Chang, Ching-Chuen Jong: HWP: a new insight into canonical signed digit. ISCAS (5) 2004: 201-204 | |
18 | Pengfei Xu, Chip-Hong Chang: Self-organizing topological tree. ISCAS (5) 2004: 732-735 | |
17 | Chip-Hong Chang, Pengfei Xu: Frequency sensitive self-organizing maps and its application in color quantization. ISCAS (5) 2004: 804-807 | |
2003 | ||
16 | EE | Shibu Menon, Chip-Hong Chang, Rui Xiao: FPGA implementation of a frequency adaptive learning SOFM for digital color still imaging. ISCAS (2) 2003: 452-455 |
15 | EE | Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang: Design of a high speed reverse converter for a new 4-moduli set residue number system. ISCAS (4) 2003: 520-523 |
14 | EE | Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan: New efficient residue-to-binary converters for 4-moduli set {2/sup n/ - 1, 2/sup n/, 2/sup n/ + 1, 2/sup n+1/ - 1}. ISCAS (4) 2003: 536-539 |
13 | EE | Mingyan Zhang, Jiangmin Gu, Chip-Hong Chang: A novel hybrid pass logic with static CMOS output drive full-adder cell. ISCAS (5) 2003: 317-320 |
12 | EE | Jiangmin Gu, Chip-Hong Chang: Ultra low voltage, low power 4-2 compressor for high speed multiplications. ISCAS (5) 2003: 321-324 |
2002 | ||
11 | EE | Chip-Hong Chang, Zhi Ye, Mingyan Zhang: Fuzzy-ART based digital watermarking scheme. APCCAS (1) 2002: 423-426 |
10 | EE | H. Tian, Siew Kei Lam, Thambipillai Srikanthan, Chip-Hong Chang: An efficient architecture for adaptive progressive thresholding. APCCAS (1) 2002: 513-516 |
9 | EE | Chip-Hong Chang, Rui Xiao, Thambipillai Srikanthan: A MSB-biased self-organizing feature map for still color image compression. APCCAS (2) 2002: 85-88 |
8 | EE | Rui Xiao, Chip-Hong Chang, Thambipillai Srikanthan: On the Initialization and Training Methods for Kohonen Self-Organizing Feature Maps in Color Image Quantization. DELTA 2002: 321-325 |
7 | EE | Jiangmin Gu, Chip-Hong Chang, Kiat Seng Yeo: An interconnect optimized floorplanning of a scalar product macrocell. ISCAS (1) 2002: 465-468 |
1999 | ||
6 | EE | Chip-Hong Chang, Bogdan J. Falkowski: Reed-Muller weight and literal vectors for NPN classification. ISCAS (1) 1999: 379-382 |
5 | EE | Bogdan J. Falkowski, Chip-Hong Chang: Optimization of partially-mixed-polarity Reed-Muller expansions. ISCAS (1) 1999: 383-386 |
1997 | ||
4 | Bogdan J. Falkowski, Chip-Hong Chang: Forward and Inverse Transformations Between Haar Spectra and Ordered Binary Decision Diagrams of Boolean Functions. IEEE Trans. Computers 46(11): 1272-1279 (1997) | |
1995 | ||
3 | EE | Chip-Hong Chang, Bogdan J. Falkowski: Flexible optimization of fixed polarity Reed-Muller expansions for multiple and output completely and incompletely specified boolean functions. ASP-DAC 1995 |
2 | Bogdan J. Falkowski, Chip-Hong Chang: Generation of Multi-Polarity Arithmetic Transform from Reduced Representation of Boolean Functions. ISCAS 1995: 2168-2171 | |
1994 | ||
1 | Bogdan J. Falkowski, Chip-Hong Chang: Efficient Algorithms for the Calculation of Arithmetic Spectrum from OBDD & Synthesis of OBDD from Arithmetic Spectrum for Incompletely Specified Boolean Functions. ISCAS 1994: 197-200 |