David Z. Pan

David Zhigang Pan

2009
77	EE	Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan: BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009)
2008
76		David Z. Pan, Gi-Joon Nam: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008 ACM 2008
75	EE	David Z. Pan, Minsik Cho: Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond. ASP-DAC 2008: 220-225
74	EE	Anand Rajaram, David Z. Pan: MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks. ASP-DAC 2008: 250-257
73	EE	Tao Luo, David Z. Pan: DPlace2.0: A stable and efficient analytical placement based on diffusion. ASP-DAC 2008: 346-351
72	EE	Tao Luo, David Newmark, David Z. Pan: Total power optimization combining placement, sizing and multi-Vt through slack distribution management. ASP-DAC 2008: 352-357
71	EE	Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan: ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction. DAC 2008: 504-509
70	EE	Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan: An integrated nonlinear placement framework with congestion and porosity aware buffer planning. DAC 2008: 702-707
69	EE	Anand Rajaram, David Z. Pan: Robust chip-level clock tree synthesis for SOC designs. DAC 2008: 720-723
68	EE	Sean X. Shi, Anand Ramalingam, Daifeng Wang, David Z. Pan: Latch Modeling for Statistical Timing Analysis. DATE 2008: 1136-1141
67	EE	Ashutosh Chakraborty, Sean X. Shi, David Z. Pan: Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices. DATE 2008: 849-855
66	EE	Tao Luo, David A. Papa, Zhuo Li, Chin-Ngai Sze, Charles J. Alpert, David Z. Pan: Pyramids: an efficient computational geometry-based approach for timing-driven placement. ICCAD 2008: 204-211
65	EE	Wooyoung Jang, Duo Ding, David Z. Pan: A voltage-frequency island aware energy optimization framework for networks-on-chip. ICCAD 2008: 264-269
64	EE	Jae-Seok Yang, David Z. Pan: Overlay aware interconnect and timing variation modeling for double patterning technology. ICCAD 2008: 488-493
63	EE	Minsik Cho, Yongchan Ban, David Z. Pan: Double patterning technology friendly detailed routing. ICCAD 2008: 506-511
62	EE	David Z. Pan, Stephen Renwick, Vivek Singh, Judy Huckabay: Nanolithography and CAD challenges for 32nm/22nm and beyond. ICCAD 2008: 6
61	EE	Minsik Cho, David Z. Pan: A high-performance droplet router for digital microfluidic biochips. ISPD 2008: 200-206
60	EE	Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang: Metal-density driven placement for cmp variation and routability. ISPD 2008: 31-38
59	EE	David Z. Pan: Synergistic modeling and optimization for nanometer IC design/manufacturing integration. SBCCI 2008: 2
58	EE	David Z. Pan: Lithography friendly routing: from construct-by-correction to correct-by-construction. SBCCI 2008: 6
57	EE	Minsik Cho, David Z. Pan: Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs. IEEE Trans. VLSI Syst. 16(12): 1713-1717 (2008)
56	EE	Minsik Cho, David Z. Pan: A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1714-1724 (2008)
55	EE	David Z. Pan, Gi-Joon Nam: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2105-2106 (2008)
54	EE	Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang: Metal-Density-Driven Placement for CMP Variation and Routability. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2145-2155 (2008)
53	EE	Patrick H. Madden, David Z. Pan: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 608-609 (2008)
52	EE	Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan: Track Routing and Optimization for Yield. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 872-882 (2008)
2007
51		Patrick H. Madden, David Z. Pan: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007 ACM 2007
50	EE	Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia: Hippocrates: First-Do-No-Harm Detailed Placement. ASP-DAC 2007: 141-146
49	EE	Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan: Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. DAC 2007: 148-153
48	EE	Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan: TROY: Track Router with Yield-driven Wire Planning. DAC 2007: 55-58
47	EE	Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan: BoxRouter 2.0: architecture and implementation of a hybrid and robust global router. ICCAD 2007: 503-508
46	EE	Peng Yu, David Z. Pan: TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction. ICCAD 2007: 847-853
45	EE	Peng Yu, David Z. Pan: A novel intensity based optical proximity correction algorithm with speedup in lithography simulation. ICCAD 2007: 854-859
44	EE	Gi-Joon Nam, Mehmet Can Yildiz, David Z. Pan, Patrick H. Madden: ISPD placement contest updates and ISPD 2007 global routing contest. ISPD 2007: 167
43	EE	Anand Ramalingam, Giri Devarayanadurg, David Z. Pan: Accurate power grid analysis with behavioral transistor network modeling. ISPD 2007: 43-50
42	EE	Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan: Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis. ISQED 2007: 398-403
41	EE	Minsik Cho, David Z. Pan: BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2130-2143 (2007)
40	EE	Haoxing Ren, David Z. Pan, Charles J. Alpert, Paul G. Villarrubia, Gi-Joon Nam: Diffusion-Based Placement Migration With Application on Legalization. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2158-2172 (2007)
39	EE	Anand Ramalingam, Anirudh Devgan, David Z. Pan: Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce. J. Low Power Electronics 3(1): 28-35 (2007)
2006
38	EE	Sean X. Shi, David Z. Pan: Wire sizing with scattering effect for nanoscale interconnection. ASP-DAC 2006: 503-508
37	EE	Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan: Robust analytical gate delay modeling for low voltage circuits. ASP-DAC 2006: 61-66
36	EE	Minsik Cho, Hongjoong Shin, David Z. Pan: Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs. ASP-DAC 2006: 765-770
35	EE	Tao Luo, David Newmark, David Z. Pan: A new LP based incremental timing driven placement for high performance designs. DAC 2006: 1115-1120
34	EE	Minsik Cho, David Z. Pan: BoxRouter: a new global router based on box expansion and progressive ILP. DAC 2006: 373-378
33	EE	Peng Yu, Sean X. Shi, David Z. Pan: Process variation aware OPC with variational lithography modeling. DAC 2006: 785-790
32	EE	Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan: An accurate sparse matrix based framework for statistical static timing analysis. ICCAD 2006: 231-236
31	EE	Sean X. Shi, Peng Yu, David Z. Pan: A unified non-rectangular device and circuit simulation model for timing and power. ICCAD 2006: 423-428
30	EE	Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri: Wire density driven global routing for CMP variation and timing. ICCAD 2006: 487-492
29	EE	Avijit Dutta, David Z. Pan: Partial Functional Manipulation Based Wirelength Minimization. ICCD 2006
28	EE	Anand Rajaram, David Z. Pan: Variation tolerant buffered clock network synthesis with cross links. ISPD 2006: 157-164
27	EE	Andrew Havlir, David Z. Pan: Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines. ISQED 2006: 171-178
26	EE	Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif: Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity. ISQED 2006: 644-649
25	EE	Anand Rajaram, David Z. Pan: Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction. ISQED 2006: 79-84
24	EE	Minsik Cho, David Z. Pan: PEAKASO: Peak-Temperature Aware Scan-Vector Optimization. VTS 2006: 52-57
2005
23	EE	Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan: Sleep transistor sizing using timing criticality and temporal currents. ASP-DAC 2005: 1094-1097
22	EE	Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong: CMP aware shuttle mask floorplanning. ASP-DAC 2005: 1111-1114
21	EE	Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong: Redundant-via enhanced maze routing for yield improvement. ASP-DAC 2005: 1148-1151
20	EE	Joydeep Mitra, Peng Yu, David Zhigang Pan: RADAR: RET-aware detailed routing using fast lithography simulations. DAC 2005: 369-372
19	EE	Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia: Diffusion-based placement migration. DAC 2005: 515-520
18		Tao Luo, Haoxing Ren, Charles J. Alpert, David Zhigang Pan: Computational geometry based placement migration. ICCAD 2005: 41-47
17		Minsik Cho, Suhail Ahmed, David Z. Pan: TACO: temperature aware clock-tree optimization. ICCAD 2005: 582-587
16	EE	Anand Rajaram, David Z. Pan, Jiang Hu: Improved algorithms for link-based non-tree clock networks for skew variability reduction. ISPD 2005: 55-62
15	EE	Haoxing Ren, David Zhigang Pan, David S. Kung: Sensitivity guided net weighting for placement-driven synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 711-721 (2005)
2004
14	EE	Haoxing Ren, David Zhigang Pan, Paul Villarrubia: True crosstalk aware incremental placement with noise map. ICCAD 2004: 402-409
13	EE	Haoxing Ren, David Zhigang Pan, David S. Kung: Sensitivity guided net weighting for placement driven synthesis. ISPD 2004: 10-17
2003
12	EE	Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni: Pushing ASIC performance in a power envelope. DAC 2003: 788-793
11	EE	Chin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan: Multilevel global placement with congestion control. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 395-409 (2003)
2002
10	EE	Chin-Chih Chang, Jason Cong, David Zhigang Pan: Physical hierarchy generation with routing congestion control. ISPD 2002: 36-41
9	EE	Jason Cong, David Zhigang Pan: Wire width planning for interconnect performance optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 319-329 (2002)
2001
8	EE	Jason Cong, David Zhigang Pan, Prasanna V. Srinivas: Improved crosstalk modeling for noise constrained interconnect optimization. ASP-DAC 2001: 373-378
7	EE	Jason Cong, David Zhigang Pan: Interconnect performance estimation models for design planning. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 739-752 (2001)
6	EE	Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan: Interconnect sizing and spacing with consideration of couplingcapacitance. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1164-1169 (2001)
1999
5	EE	Jason Cong, David Zhigang Pan: Interconnect Delay Estimation Models for Synthesis and Design Planning. ASP-DAC 1999: 97-100
4	EE	Jason Cong, David Zhigang Pan: Interconnect Estimation and Dlanning for Deep Submicron Designs. DAC 1999: 507-510
3	EE	Jason Cong, Tianming Kong, David Zhigang Pan: Buffer block planning for interconnect-driven floorplanning. ICCAD 1999: 358-363
1997
2	EE	Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo: Interconnect design for deep submicron ICs. ICCAD 1997: 478-485
1	EE	Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan: Global interconnect sizing and spacing with consideration of coupling capacitance. ICCAD 1997: 628-633

Coauthor Index

1	Suhail Ahmed	[17]
2	Charles J. Alpert	[18] [19] [40] [50] [66]
3	Yongchan Ban	[63] [71]
4	Ashutosh Chakraborty	[67] [70]
5	Chin-Chih Chang	[10] [11]
6	Yao-Wen Chang	[54] [60]
7	Jian Chen	[42]
8	Tung-Chieh Chen	[54] [60] [70]
9	Minsik Cho	[17] [24] [30] [34] [36] [41] [47] [48] [52] [54] [56] [57] [60] [61] [63] [71] [75] [77]
10	John M. Cohn	[12]
11	Jason Cong	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
12	Giri Devarayanadurg	[43]
13	Anirudh Devgan	[23] [37] [39]
14	Duo Ding	[65]
15	Avijit Dutta	[29]
16	Andrew Havlir	[27]
17	Lei He	[1] [2] [6]
18	Jiang Hu	[16]
19	Li-Da Huang	[21]
20	Judy Huckabay	[62]
21	Wooyoung Jang	[65]
22	Kei-Yong Khoo	[2]
23	Sreekumar V. Kodakara	[37]
24	Cheng-Kok Koh	[1] [2] [6]
25	Tianming Kong	[3]
26	Sarvesh H. Kulkarni	[12]
27	David S. Kung	[12] [13] [15]
28	Zhuo Li	[66]
29	Frank Liu	[26]
30	Katrina Lu	[47] [77]
31	Tao Luo	[18] [35] [66] [72] [73]
32	Patrick H. Madden	[44] [51] [53]
33	Joydeep Mitra	[20]
34	Gi-Joon Nam	[32] [40] [44] [50] [55] [76]
35	Sani R. Nassif	[26] [32] [49]
36	David Newmark	[35] [72]
37	Michael Orshansky	[32] [49]
38	David A. Papa	[66]
39	Ruchir Puri	[12] [30] [48] [52]
40	Anand Rajaram	[16] [25] [28] [42] [69] [74]
41	Anand Ramalingam	[23] [26] [32] [37] [39] [43] [49] [68]
42	Haoxing Ren	[13] [14] [15] [18] [19] [40] [50]
43	Stephen Renwick	[62]
44	Ninghy Shi	[42]
45	Sean X. Shi	[31] [33] [38] [67] [68]
46	Hongjoong Shin	[36]
47	Ashish Kumar Singh	[32] [49]
48	Vivek Singh	[62]
49	Prasanna V. Srinivas	[8]
50	Ashish Srivastava	[12]
51	Leon Stok	[12]
52	Dennis Sylvester	[12]
53	Chin-Ngai Sze	[66]
54	Ruiqi Tian	[22]
55	Paul G. Villarrubia (Paul Villarrubia)	[14] [19] [40] [50]
56	Daifeng Wang	[68]
57	Martin D. F. Wong (D. F. Wong)	[21] [22]
58	Hua Xiang	[30] [48] [52]
59	Gang Xu	[21] [22]
60	Jae-Seok Yang	[64]
61	Joon-Sung Yang	[42]
62	Mehmet Can Yildiz	[44]
63	Peng Yu	[20] [31] [33] [45] [46]
64	Kun Yuan	[47] [71] [77]
65	Xin Yuan	[11]
66	Bin Zhang	[23]

Colors in the list of coauthors