| 2007 |
|---|
| 11 | EE | Xin Li,
Jiayong Le,
Padmini Gopalakrishnan,
Lawrence T. Pileggi:
Asymptotic Probability Extraction for Nonnormal Performance Distributions.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 16-37 (2007) |
| 10 | EE | Xin Li,
Padmini Gopalakrishnan,
Yang Xu,
Lawrence T. Pileggi:
Robust Analog/RF Circuit Design With Projection-Based Performance Modeling.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 2-15 (2007) |
| 2006 |
|---|
| 9 | EE | Padmini Gopalakrishnan,
Xin Li,
Lawrence T. Pileggi:
Architecture-aware FPGA placement using metric embedding.
DAC 2006: 460-465 |
| 2004 |
|---|
| 8 | EE | Xin Li,
Yang Xu,
Peng Li,
Padmini Gopalakrishnan,
Lawrence T. Pileggi:
A frequency relaxation approach for analog/RF system-level simulation.
DAC 2004: 842-847 |
| 7 | EE | Aneesh Koorapaty,
V. Kheterpal,
Padmini Gopalakrishnan,
M. Fu,
Lawrence T. Pileggi:
Exploring Logic Block Granularity for Regular Fabrics.
DATE 2004: 468-473 |
| 6 | EE | Xin Li,
Jiayong Le,
Padmini Gopalakrishnan,
Lawrence T. Pileggi:
Asymptotic probability extraction for non-normal distributions of circuit performance.
ICCAD 2004: 2-9 |
| 5 | EE | Xin Li,
Padmini Gopalakrishnan,
Yang Xu,
Lawrence T. Pileggi:
Robust analog/RF circuit design with projection-based posynomial modeling.
ICCAD 2004: 855-862 |
| 4 | EE | Thomas J. Vogels,
Thomas Zanon,
Rao Desineni,
R. D. (Shawn) Blanton,
Wojciech Maly,
Jason G. Brown,
Jeffrey E. Nelson,
Y. Fei,
X. Huang,
Padmini Gopalakrishnan,
Mahim Mishra,
V. Rovner,
S. Tiwary:
Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations.
ITC 2004: 508-517 |
| 2003 |
|---|
| 3 | EE | Lawrence T. Pileggi,
Herman Schmit,
Andrzej J. Strojwas,
Padmini Gopalakrishnan,
V. Kheterpal,
Aneesh Koorapaty,
Chetan Patel,
V. Rovner,
K. Y. Tong:
Exploring regular fabrics to optimize the performance-cost trade-off.
DAC 2003: 782-787 |
| 2002 |
|---|
| 2 | EE | Padmini Gopalakrishnan,
Altan Odabasioglu,
Lawrence T. Pileggi,
Salil Raje:
An analysis of the wire-load model uncertainty problem.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 23-31 (2002) |
| 2001 |
|---|
| 1 | EE | Padmini Gopalakrishnan,
Altan Odabasioglu,
Lawrence T. Pileggi,
Salil Raje:
Overcoming wireload model uncertainty during physical design.
ISPD 2001: 182-189 |
