Volume 27,
Number 1,
January 2008
- Enrico Macii:
Editorial.
1-2
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- Andrew B. Kahng, Kambiz Samadi:
CMP Fill Synthesis: A Survey of Recent Studies.
3-19
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- Josep Carmona, Jordi Cortadella:
Encoding Large Asynchronous Controllers With ILP Techniques.
20-33
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- Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi:
Two-Dimensional Schemes for Clocking/Timing of QCA Circuits.
34-44
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- Shrirang K. Karandikar, Sachin S. Sapatnekar:
Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem.
45-58
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- Ting Mei, Jaijeet S. Roychowdhury:
A Time-Domain Oscillator Envelope Tracking Algorithm Employing Dual Phase Conditions.
59-69
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- Chris C. N. Chu, Yiu-Chung Wong:
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design.
70-83
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- Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger:
Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards.
84-95
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- Amit Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha:
System-Level Dynamic Thermal Management for High-Performance Microprocessors.
96-108
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- Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen:
A Reactive and Cycle-True IP Emulator for MPSoC Exploration.
109-122
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- Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras:
Experimental Characterization of CMOS Interconnect Open Defects.
123-136
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- Irith Pomeranz, Sudhakar M. Reddy:
Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation.
137-146
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- Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Neelanjan Mukherjee, Mark Kassab:
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector.
147-159
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- Jaskirat Singh, Sachin S. Sapatnekar:
A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations.
160-173
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- Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy:
Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias.
174-183
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- Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Fixing Design Errors With Counterexamples and Resynthesis.
184-188
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- Sushanta K. Mandal, Shamik Sural, Amit Patra:
ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs.
188-192
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- Irith Pomeranz, Sudhakar M. Reddy:
Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits.
193-197
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- Weixin Wu, Michael S. Hsiao:
Mining Global Constraints With Domain Knowledge for Improving Bounded Sequential Equivalence Checking.
197-201
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Volume 27,
Number 2,
February 2008
- Javid Jaffari, Mohab Anis:
Variability-Aware Bulk-MOS Device Design.
205-216
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- R. Mahesh, A. Prasad Vinod:
A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters.
217-229
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- Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma:
Defocus-Aware Leakage Estimation and Control.
230-240
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- Ja Chun Ku, Yehea I. Ismail:
Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies.
241-248
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- Ning Dong, Jaijeet S. Roychowdhury:
General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations.
249-264
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- Alexander Heldring, Juan M. Rius, José Maria Tamayo, Josep Parrón:
Compressed Block-Decomposition Algorithm for Fast Capacitance Extraction.
265-271
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- Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw:
A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance.
272-285
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- Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin:
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning.
286-294
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- Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar:
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation.
295-308
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- Shantanu Dutt, Vinay Verma, Vishal Suthar:
Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing.
309-326
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- Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker:
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
327-338
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- Haralampos-G. D. Stratigopoulos, Yiorgos Makris:
Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing.
339-351
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- Zhanglei Wang, Krishnendu Chakrabarty:
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns.
352-365
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- Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke:
Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog.
366-379
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- Ilya Wagner, Valeria Bertacco, Todd M. Austin:
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors.
380-393
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- Hiren D. Patel, Sandeep K. Shukla:
On Cosimulating Multiple Abstraction-Level System-Level Models.
394-398
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- Irith Pomeranz, Sudhakar M. Reddy:
Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test.
398-403
Electronic Edition (link) BibTeX
- Aleksandra Sesic, Stanisa Dautovic, Veljko Malbasa:
Dynamic Power Management of a System With a Two-Priority Request Queue Using Probabilistic-Model Checking.
403-407
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Volume 27,
Number 3,
March 2008
- Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh:
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration.
409-422
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- Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown:
Scalable Synthesis and Clustering Techniques Using Decision Diagrams.
423-435
Electronic Edition (link) BibTeX
- Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, C. Negrevergne:
Quantum Circuit Simplification and Level Compaction.
436-444
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- Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations.
445-455
Electronic Edition (link) BibTeX
- Kin Cheong Sou, Alexandre Megretski, Luca Daniel:
A Quasi-Convex Optimization Approach to Parameterized Model Order Reduction.
456-469
Electronic Edition (link) BibTeX
- Ngai Wong:
Efficient Positive-Real Balanced Truncation of Symmetric Systems Via Cross-Riccati Equations.
470-480
Electronic Edition (link) BibTeX
- Sarvesh H. Kulkarni, D. M. Sylvester, David T. Blaauw:
Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias.
481-494
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- Baolin Yang, Yu Zhu, Ali Bouaricha, Joel R. Phillips:
Applications of the Multi-Interval Chebyshev Collocation Method in RF Circuit Simulation.
495-507
Electronic Edition (link) BibTeX
- Peter Hallschmid, Resve Saleh:
Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs.
508-515
Electronic Edition (link) BibTeX
- Seda Ogrenci Memik, Rajarshi Mukherjee, Min Ni, Jieyi Long:
Optimizing Thermal Sensor Allocation for Microprocessors.
516-527
Electronic Edition (link) BibTeX
- Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk:
CHIPS: Custom Hardware Instruction Processor Synthesis.
528-541
Electronic Edition (link) BibTeX
- Hristo Nikolov, Todor Stefanov, Ed F. Deprettere:
Systematic and Automated Multiprocessor System Design, Programming, and Implementation.
542-555
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- Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar:
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis.
556-569
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- Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda:
An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores.
570-574
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- Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub:
A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform.
574-578
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- Chaeho Chung, Soobum Lee, Byung Man Kwak, Gawon Kim, Joungho Kim:
A Delay Line Circuit Design for Crosstalk Minimization Using Genetic Algorithm.
578-583
Electronic Edition (link) BibTeX
- Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy:
On Complete Functional Broadside Tests for Transition Faults.
583-587
Electronic Edition (link) BibTeX
Volume 27,
Number 4,
April 2008
- David Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer:
Statistical Timing Analysis: From Basic Principles to State of the Art.
589-607
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- Patrick H. Madden, David Z. Pan:
Guest Editorial.
608-609
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- Vishal Khandelwal, Ankur Srivastava:
Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation.
610-620
Electronic Edition (link) BibTeX
- Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong:
Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm.
621-632
Electronic Edition (link) BibTeX
- Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong:
Fast Dummy-Fill Density Analysis With Coupling Constraints.
633-642
Electronic Edition (link) BibTeX
- Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang:
Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs.
643-653
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- Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang:
Effective Wire Models for X-Architecture Placement.
654-658
Electronic Edition (link) BibTeX
- Cheoljoo Jeong, Steven M. Nowick:
Technology Mapping and Cell Merger for Asynchronous Threshold Networks.
659-672
Electronic Edition (link) BibTeX
- Seok-Won Seong, Prabhat Mishra:
Bitmask-Based Code Compression for Embedded Systems.
673-685
Electronic Edition (link) BibTeX
- Ryan Fung, Vaughn Betz, William Chow:
Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations.
686-697
Electronic Edition (link) BibTeX
- Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew:
GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials.
698-711
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- Ying Wei, Alex Doboli:
Structural Macromodeling of Analog Circuits Through Model Decoupling and Transformation.
712-725
Electronic Edition (link) BibTeX
- Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, Xianlong Hong:
Fashion: A Fast and Accurate Solution to Global Routing Problem.
726-737
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- Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen:
Power Grid Analysis and Optimization Using Algebraic Multigrid.
738-751
Electronic Edition (link) BibTeX
- Dmitri Maslov, Sean M. Falconer, Michele Mosca:
Quantum Circuit Placement.
752-763
Electronic Edition (link) BibTeX
- Neil Kettle, Andy King:
An Anytime Algorithm for Generalized Symmetry Detection in ROBDDs.
764-777
Electronic Edition (link) BibTeX
Volume 27,
Number 5,
May 2008
- Paolo Maffezzoni:
Unified Computation of Parameter Sensitivity and Signal-Injection Sensitivity in Nonlinear Oscillators.
781-790
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- Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi:
Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach.
791-802
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- Natasa Miskov-Zivanov, Diana Marculescu:
Modeling and Optimization for Soft-Error Reliability of Sequential Circuits.
803-816
Electronic Edition (link) BibTeX
- S. Srivastava, J. Roychowdhury:
Independent and Interdependent Latch Setup/Hold Time Characterization via Newton-Raphson Solution and Euler Curve Tracking of State-Transition Equations.
817-830
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- Xin Li, Yaping Zhan, Lawrence T. Pileggi:
Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits.
831-843
Electronic Edition (link) BibTeX
- Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han:
Full-Chip Routing Considering Double-Via Insertion.
844-857
Electronic Edition (link) BibTeX
- Song Chen, Takeshi Yoshimura:
Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs.
858-871
Electronic Edition (link) BibTeX
- Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan:
Track Routing and Optimization for Yield.
872-882
Electronic Edition (link) BibTeX
- Bo Hu, C.-J. Richard Shi:
Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis.
883-892
Electronic Edition (link) BibTeX
- Diana Marculescu, Siddharth Garg:
Process-Driven Variability Analysis of Single and Multiple Voltage-Frequency Island Latency-Constrained Systems.
893-905
Electronic Edition (link) BibTeX
- Claudio Pinello, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli:
Fault-Tolerant Distributed Deployment of Embedded Control Software.
906-919
Electronic Edition (link) BibTeX
- Erkan Acar, Sule Ozev:
Defect-Oriented Testing of RF Circuits.
920-931
Electronic Edition (link) BibTeX
- Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Improving the Resolution of Single-Delay-Fault Diagnosis.
932-945
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
On the Saturation of n-Detection Test Generation by Different Definitions With Increased n.
946-957
Electronic Edition (link) BibTeX
- Jeong-Ho Han, In-Cheol Park:
FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient.
958-962
Electronic Edition (link) BibTeX
- Xiaojun Ma, Fabrizio Lombardi:
Synthesis of Tile Sets for DNA Self-Assembly.
963-967
Electronic Edition (link) BibTeX
- Bhaskar Pal, Ansuman Banerjee, Arnab Sinha, Pallab Dasgupta:
Accelerating Assertion Coverage With Adaptive Testbenches.
967-972
Electronic Edition (link) BibTeX
- Soheil Samii, Mikko Selkälä, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng:
Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling.
973-977
Electronic Edition (link) BibTeX
- Gülin Tulunay, Sina Balkir:
A Synthesis Tool for CMOS RF Low-Noise Amplifiers.
977-982
Electronic Edition (link) BibTeX
Volume 27,
Number 6,
June 2008
- Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang:
Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time Analysis.
985-998
Electronic Edition (link) BibTeX
- Dong Xiang, Yang Zhao, K. Chakrabarty, Hideo Fujiwara:
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST.
999-1012
Electronic Edition (link) BibTeX
- Levent Aksoy, Eduardo da Costa, Paulo F. Flores, José Monteiro:
Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications.
1013-1026
Electronic Edition (link) BibTeX
- Javid Jaffari, Mohab Anis:
Statistical Thermal Profile Considering Process Variations: Analysis and Applications.
1027-1040
Electronic Edition (link) BibTeX
- Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi:
Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations.
1041-1054
Electronic Edition (link) BibTeX
- Zhe-Wei Jiang, Yao-Wen Chang:
An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing.
1055-1065
Electronic Edition (link) BibTeX
- Jarrod A. Roy, Igor L. Markov:
High-Performance Routing at the Nanometer Scale.
1066-1077
Electronic Edition (link) BibTeX
- Pramod Chandraiah, Rainer Dömer:
Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding.
1078-1090
Electronic Edition (link) BibTeX
- Tarvo Raudvere, Ingo Sander, Axel Jantsch:
Application and Verification of Local Nonsemantic-Preserving Transformations in System Design.
1091-1103
Electronic Edition (link) BibTeX
- Wei-Shun Chuang, Shiu-Ting Lin, Wei-Chih Liu, James Chien-Mo Li:
Diagnosis of Multiple Scan Chain Timing Faults.
1104-1116
Electronic Edition (link) BibTeX
- S. Saqib Khursheed, Urban Ingelsson, Paul M. Rosinger, Bashir M. Al-Hashimi, Peter Harrod:
Bridging Fault Test Method With Adaptive Power Management Awareness.
1117-1127
Electronic Edition (link) BibTeX
- Afshin Abdollahi, Massoud Pedram:
Symmetry Detection and Boolean Matching Utilizing a Signature-Based Canonical Form of Boolean Functions.
1128-1137
Electronic Edition (link) BibTeX
- Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler:
Automatic Fault Localization for Property Checking.
1138-1149
Electronic Edition (link) BibTeX
- Brajesh Kumar Kaushik, Sankar Sarkar:
Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects.
1150-1154
Electronic Edition (link) BibTeX
- Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie:
Register File Power Reduction Using Bypass Sensitive Compiler.
1155-1159
Electronic Edition (link) BibTeX
- Lin Yuan, Gang Qu, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli:
An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting.
1159-1164
Electronic Edition (link) BibTeX
Volume 27,
Number 7,
July 2008
- Vijay D'Silva, Daniel Kroening, Georg Weissenbacher:
A Survey of Automated Techniques for Formal Software Verification.
1165-1178
Electronic Edition (link) BibTeX
- R. Castro-López, Oscar Guerra, Elisenda Roca, Francisco V. Fernández:
An Integrated Layout-Synthesis Approach for Analog ICs.
1179-1189
Electronic Edition (link) BibTeX
- Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa:
Logic Minimization and Testability of 2-SPP Networks.
1190-1202
Electronic Edition (link) BibTeX
- Lei Cheng, Deming Chen, Martin D. F. Wong:
DDBDD: Delay-Driven BDD Synthesis for FPGAs.
1203-1213
Electronic Edition (link) BibTeX
- Taehoon Kim, Yungseon Eo:
Analytical CAD Models for the Signal Transients and Crosstalk Noise of Inductance-Effect-Prominent Multicoupled RLC Interconnect Lines.
1214-1227
Electronic Edition (link) BibTeX
- Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang:
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints.
1228-1240
Electronic Edition (link) BibTeX
- Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu:
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion.
1241-1252
Electronic Edition (link) BibTeX
- Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He:
Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations.
1253-1263
Electronic Edition (link) BibTeX
- Soner Yaldiz, Alper Demir, Serdar Tasiran:
Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study.
1264-1277
Electronic Edition (link) BibTeX
- Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low-Power Test Data Application in EDT Environment Through Decompressor Freeze.
1278-1290
Electronic Edition (link) BibTeX
- Sari Onaissi, Farid N. Najm:
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners.
1291-1304
Electronic Edition (link) BibTeX
- Daniel Große, Ulrich Kühne, Rolf Drechsler:
Analyzing Functional Coverage in Bounded Model Checking.
1305-1314
Electronic Edition (link) BibTeX
- Xiaoxi Xu, Cheng-Chew Lim:
Using Transfer-Resource Graph for Software-Based Verification of System-on-Chip.
1315-1328
Electronic Edition (link) BibTeX
- Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille:
On Acceleration of SAT-Based ATPG for Industrial Designs.
1329-1333
Electronic Edition (link) BibTeX
- Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability.
1333-1338
Electronic Edition (link) BibTeX
- Jing-Ling Yang, Qiang Xu:
State-Sensitive X-Filling Scheme for Scan Capture Power Reduction.
1338-1343
Electronic Edition (link) BibTeX
- Hao Zheng, Jared Ahrens, Tian Xia:
A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification.
1343-1347
Electronic Edition (link) BibTeX
Volume 27,
Number 8,
August 2008
- Jason Cong, Min Xie:
A Robust Mixed-Size Legalization and Detailed Placement Algorithm.
1349-1362
Electronic Edition (link) BibTeX
- Chih-Hung Liu, Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Yao-Wen Chang, Sy-Yen Kuo, Shih-Yi Yuan, Yu-Wei Chen:
An Efficient Graph-Based Algorithm for ESD Current Path Analysis.
1363-1375
Electronic Edition (link) BibTeX
- Maharaj Mukherjee, Kanad Chakraborty:
A Randomized Greedy Method for Rectangular-Pattern Fill Problems.
1376-1384
Electronic Edition (link) BibTeX
- Uday Padmanabhan, Janet Meiling Wang, Jiang Hu:
Robust Clock Tree Routing in the Presence of Process Variations.
1385-1397
Electronic Edition (link) BibTeX
- Peter Spindler, Ulf Schlichtmann, Frank M. Johannes:
Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model.
1398-1411
Electronic Edition (link) BibTeX
- Giovanni Agosta, Francesco Bruschi, Donatella Sciuto:
Static Analysis of Transaction-Level Communication Models.
1412-1424
Electronic Edition (link) BibTeX
- Karam S. Chatha, Krishnan Srinivasan, Goran Konjevod:
Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures.
1425-1438
Electronic Edition (link) BibTeX
- Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt:
Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications.
1439-1452
Electronic Edition (link) BibTeX
- Ozgur Sinanoglu, Tsvetomir Petrov:
Isolation Techniques for Soft Cores.
1453-1466
Electronic Edition (link) BibTeX
- Changjiu Xian, Yung-Hsiang Lu, Zhiyuan Li:
Dynamic Voltage Scaling for Multitasking Real-Time Systems With Uncertain Execution Time.
1467-1478
Electronic Edition (link) BibTeX
- Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick, Russ Joseph:
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management.
1479-1492
Electronic Edition (link) BibTeX
- Soumya Pandit, Sumit K. Bhattacharya, Chittaranjan A. Mandal, Amit Patra:
A Fast Exploration Procedure for Analog High-Level Specification Translation.
1493-1497
Electronic Edition (link) BibTeX
- King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, Xinyi Zhang:
Dual-Vdd Buffer Insertion for Power Reduction.
1498-1502
Electronic Edition (link) BibTeX
- Shuai Wang, Jie Hu, Sotirios G. Ziavras:
Self-Adaptive Data Caches for Soft-Error Reliability.
1503-1507
Electronic Edition (link) BibTeX
- Wenjian Yu, Xiren Wang, Zuochang Ye, Zeyi Wang:
Efficient Extraction of Frequency-Dependent Substrate Parasitics Using Direct Boundary Element Method.
1508-1513
Electronic Edition (link) BibTeX
- Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking.
1513-1517
Electronic Edition (link) BibTeX
Volume 27,
Number 9,
September 2008
- Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Sensitivity Analysis for Oscillators.
1521-1534
Electronic Edition (link) BibTeX
- Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi:
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models.
1535-1544
Electronic Edition (link) BibTeX
- Y.-J. J. Yang, C.-W. Kuo:
Generating Scalable and Modular Macromodels for Microchannels Using the Galerkin-Based Technique.
1545-1554
Electronic Edition (link) BibTeX
- Hassan Hassan, Mohab Anis, Mohamed I. Elmasry:
Input Vector Reordering for Leakage Power Reduction in FPGAs.
1555-1564
Electronic Edition (link) BibTeX
- Aijiao Cui, Chip-Hong Chang, Sofiène Tahar:
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level.
1565-1570
Electronic Edition (link) BibTeX
- Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng:
Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process.
1571-1582
Electronic Edition (link) BibTeX
- Hiran Tennakoon, Carl Sechen:
Nonconvex Gate Delay Modeling and Delay Optimization.
1583-1594
Electronic Edition (link) BibTeX
- Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram:
Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method.
1595-1606
Electronic Edition (link) BibTeX
- Ulrich Brenner, Markus Struzyna, Jens Vygen:
BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms.
1607-1620
Electronic Edition (link) BibTeX
- Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Few-Juh Huang, T.-Y. Liu:
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs.
1621-1634
Electronic Edition (link) BibTeX
- Andrew B. Kahng, Chul-Hong Park, Xu Xu:
Fast Dual-Graph-Based Hotspot Filtering.
1635-1642
Electronic Edition (link) BibTeX
- T.-H. Lee, T.-C. Wang:
Congestion-Constrained Layer Assignment for Via Minimization in Global Routing.
1643-1656
Electronic Edition (link) BibTeX
- Munkang Choi, Linda S. Milor:
Diagnosis of Optical Lithography Faults With Product Test Sets.
1657-1669
Electronic Edition (link) BibTeX
- Fu-Ching Yang, Wen-Kai Huang, Jing-Kun Zhong, Ing-Jer Huang:
Automatic Verification of External Interrupt Behaviors for Microprocessor Design.
1670-1683
Electronic Edition (link) BibTeX
- J.-C. Guo, Y.-M. Lin:
A Compact RF CMOS Modeling for Accurate High-Frequency Noise Simulation in Sub-100-nm MOSFETs.
1684-1688
Electronic Edition (link) BibTeX
- Jayawant Kakade, Dimitrios Kagaris, Dhiraj K. Pradhan:
Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs.
1689-1692
Electronic Edition (link) BibTeX
- H.-C. Liang, P.-H. Huang, Y.-F. Tang:
Testing Transition Delay Faults in Modified Booth Multipliers.
1693-1697
Electronic Edition (link) BibTeX
Volume 27,
Number 10,
October 2008
- Wayne Wolf, Ahmed Amine Jerraya, Grant Martin:
Multiprocessor System-on-Chip (MPSoC) Technology.
1701-1713
Electronic Edition (link) BibTeX
- Minsik Cho, David Z. Pan:
A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips.
1714-1724
Electronic Edition (link) BibTeX
- Nishant Patil, Jie Deng, Albert Lin, H.-S. Philip Wong, Subhasish Mitra:
Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits.
1725-1736
Electronic Edition (link) BibTeX
- Alessandro Cimatti, Marco Roveri, Stefano Tonetta:
Symbolic Compilation of PSL.
1737-1750
Electronic Edition (link) BibTeX
- Yu Hu, Victor Shih, Rupak Majumdar, Lei He:
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs.
1751-1760
Electronic Edition (link) BibTeX
- Ajay K. Verma, Philip Brisk, Paolo Ienne:
Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits.
1761-1774
Electronic Edition (link) BibTeX
- Osama Neiroukh, Stephen A. Edwards, Xiaoyu Song:
Transforming Cyclic Circuits Into Acyclic Equivalents.
1775-1787
Electronic Edition (link) BibTeX
- Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodrag Potkonjak, Majid Sarrafzadeh:
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing.
1788-1797
Electronic Edition (link) BibTeX
- Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram:
Charge Recycling in Power-Gated CMOS Circuits.
1798-1811
Electronic Edition (link) BibTeX
- Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Amit Goel:
A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations.
1812-1825
Electronic Edition (link) BibTeX
- Khaled R. Heloue, Farid N. Najm:
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models.
1826-1839
Electronic Edition (link) BibTeX
- Andrew Labun, Karan Jagjitkumar:
Rapid Detailed Temperature Estimation for Highly Coupled IC Interconnect.
1840-1851
Electronic Edition (link) BibTeX
- Jin Sun, Jun Li, Dongsheng Ma, Janet Meiling Wang:
Chebyshev Affine-Arithmetic-Based Parametric Yield Prediction Under Limited Descriptions of Uncertainty.
1852-1865
Electronic Edition (link) BibTeX
- Chen-Ling Chou, Ümit Y. Ogras, Radu Marculescu:
Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels.
1866-1879
Electronic Edition (link) BibTeX
- Guo Yu, Wei Dong, Zhuo Feng, Peng Li:
Statistical Static Timing Analysis Considering Process Variation Model Uncertainty.
1880-1890
Electronic Edition (link) BibTeX
- Kian Haghdad, Mohab Anis:
Design-Specific Optimization Considering Supply and Threshold Voltage Variations.
1891-1901
Electronic Edition (link) BibTeX
Volume 27,
Number 11,
November 2008
- Tao Xu, Krishnendu Chakrabarty:
A Droplet-Manipulation Method for Achieving High-Throughput in Cross-Referencing-Based Digital Microfluidic Biochips.
1905-1917
Electronic Edition (link) BibTeX
- Yang Yi, Peng Li, Vivek Sarin, Weiping Shi:
A Preconditioned Hierarchical Algorithm for Impedance Extraction of Three-Dimensional Structures With Multiple Dielectrics.
1918-1927
Electronic Edition (link) BibTeX
- Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips.
1928-1941
Electronic Edition (link) BibTeX
- Yung-Chih Chen, Chun-Yao Wang:
An Implicit Approach to Minimizing Range-Equivalent Circuits.
1942-1955
Electronic Edition (link) BibTeX
- Jun Seomun, Jae-Hyun Kim, Youngsoo Shin:
Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits.
1956-1968
Electronic Edition (link) BibTeX
- Yongsoo Joo, Yongseok Choi, Jaehyun Park, Chanik Park, Sung Woo Chung, Eui-Young Chung, Naehyuck Chang:
Energy and Performance Optimization of Demand Paging With OneNAND Flash.
1969-1982
Electronic Edition (link) BibTeX
- Mohamed H. Abu-Rahma, Mohab Anis:
A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations.
1983-1995
Electronic Edition (link) BibTeX
- Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method.
1996-2006
Electronic Edition (link) BibTeX
- Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Lee, Yao-Wen Chang:
Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs.
2007-2016
Electronic Edition (link) BibTeX
- Michael D. Moffitt:
MaizeRouter: Engineering an Effective Global Router.
2017-2026
Electronic Edition (link) BibTeX
- Seda Ogrenci Memik, Nikolaos Bellas, Somsubhra Mondal:
Presynthesis Area Estimation of Reconfigurable Streaming Accelerators.
2027-2038
Electronic Edition (link) BibTeX
- Seongmoon Wang, Wenlong Wei:
An Efficient Unknown BlockingScheme for Low Control Data Volume and High Observability.
2039-2052
Electronic Edition (link) BibTeX
- M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli:
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories.
2053-2067
Electronic Edition (link) BibTeX
- Minh D. Nguyen, Max Thalmaier, Markus Wedler, J. Bormann, Dominik Stoffel, Wolfgang Kunz:
Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants.
2068-2082
Electronic Edition (link) BibTeX
- Sertac Cinel, Cüneyt F. Bazlamaçci:
A Distributed Heuristic Algorithm for the Rectilinear Steiner Minimal Tree Problem.
2083-2087
Electronic Edition (link) BibTeX
- Hyunjin Kim, Hyejeong Hong, Hong-Sik Kim, Jin-Ho Ahn, Sungho Kang:
Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric.
2088-2092
Electronic Edition (link) BibTeX
- Ho Fai Ko, Nicola Nicolici:
Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test.
2092-2097
Electronic Edition (link) BibTeX
- Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen-Ching Wu:
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.
2097-2101
Electronic Edition (link) BibTeX
Volume 27,
Number 12,
December 2008
- David Z. Pan, Gi-Joon Nam:
Guest Editorial.
2105-2106
Electronic Edition (link) BibTeX
- Stephen Plaza, Igor L. Markov, Valeria Bertacco:
Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring.
2107-2119
Electronic Edition (link) BibTeX
- Hosung Kim, John Lillis:
A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs.
2120-2132
Electronic Edition (link) BibTeX
- Jason Cong, Guojie Luo, E. Radke:
Highly Efficient Gradient Computation for Density-Constrained Analytical Placement.
2133-2144
Electronic Edition (link) BibTeX
- Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang:
Metal-Density-Driven Placement for CMP Variation and Routability.
2145-2155
Electronic Edition (link) BibTeX
- David A. Papa, Tao Luo, Michael D. Moffitt, Chin-Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm.
2156-2168
Electronic Edition (link) BibTeX
- Jieyi Long, Hai Zhou, Seda Ogrenci Memik:
EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm.
2169-2182
Electronic Edition (link) BibTeX
- Yifang Liu, Jiang Hu, Weiping Shi:
Buffering Interconnect for Multicore Processor Designs.
2183-2196
Electronic Edition (link) BibTeX
- Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao:
Fast and Optimal Redundant Via Insertion.
2197-2208
Electronic Edition (link) BibTeX
- Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann:
The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis.
2209-2222
Electronic Edition (link) BibTeX
- David Walter, Scott Little, Chris J. Myers, Nicholas Seegmiller, Tomohiro Yoneda:
Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods.
2223-2235
Electronic Edition (link) BibTeX
- Tomasz S. Czajkowski, Stephen Dean Brown:
Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs.
2236-2249
Electronic Edition (link) BibTeX
- Roxana Ionutiu, Joost Rommes, Athanasios C. Antoulas:
Passivity-Preserving Model Reduction Using Dominant Spectral-Zero Interpolation.
2250-2263
Electronic Edition (link) BibTeX
- Lin Xie, Azadeh Davoodi:
Robust Estimation of Timing Yield With Partial Statistical Information on Process Variations.
2264-2276
Electronic Edition (link) BibTeX
- Rebecca L. Collins, Luca P. Carloni:
Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems.
2277-2290
Electronic Edition (link) BibTeX
- Chunrong Song, Spyros Tragoudas:
Identification of Critical Executable Paths at the Architectural Level.
2291-2302
Electronic Edition (link) BibTeX
- Ozgur Sinanoglu:
Scan Architecture With Align-Encode.
2303-2316
Electronic Edition (link) BibTeX
- Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar:
Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools.
2317-2330
Electronic Edition (link) BibTeX
Copyright © Sun May 17 00:23:19 2009
by Michael Ley (ley@uni-trier.de)