| 2008 |
|---|
| 6 | EE | Shantanu Dutt,
Vinay Verma,
Vishal Suthar:
Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 309-326 (2008) |
| 2006 |
|---|
| 5 | EE | Vishal Suthar,
Shantanu Dutt:
Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults.
DATE 2006: 1165-1170 |
| 4 | EE | Shantanu Dutt,
Huan Ren,
Fenghua Yuan,
Vishal Suthar:
A network-flow approach to timing-driven incremental placement for ASICs.
ICCAD 2006: 375-382 |
| 3 | EE | Vishal Suthar,
Shantanu Dutt:
Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions.
VTS 2006: 36-43 |
| 2005 |
|---|
| 2 | EE | Vishal Suthar,
Shantanu Dutt:
High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping.
ACM Great Lakes Symposium on VLSI 2005: 78-83 |
| 2004 |
|---|
| 1 | EE | Vinay Verma,
Shantanu Dutt,
Vishal Suthar:
Efficient on-line testing of FPGAs with provable diagnosabilities.
DAC 2004: 498-503 |
