2008 |
25 | EE | David Blaauw,
Kaviraj Chopra,
Ashish Srivastava,
Louis Scheffer:
Statistical Timing Analysis: From Basic Principles to State of the Art.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 589-607 (2008) |
2007 |
24 | EE | Louis Scheffer:
CAD Implications of New Interconnect Technologies.
DAC 2007: 576-581 |
23 | EE | David Cross,
Eric Nequist,
Louis Scheffer:
A DFM aware, space based router.
ISPD 2007: 171-172 |
22 | EE | Louis Scheffer,
Lars Liebmann,
Riko Rakojcic,
David White:
Rules vs tools: what's the right way to address IC manufacturing complexity?
ISPD 2007: 75-76 |
21 | EE | Igor L. Markov,
Louis Scheffer,
Dirk Stroobandt:
Special issue on System-Level Interconnect Prediction.
Integration 40(4): 381 (2007) |
2006 |
20 | | Louis Scheffer:
Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006
ACM 2006 |
19 | EE | Louis Scheffer:
An overview of on-chip interconnect variation.
SLIP 2006: 27-28 |
2005 |
18 | | Patrick Groeneveld,
Louis Scheffer:
Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005
ACM 2005 |
2004 |
17 | | Louis Scheffer,
Igor L. Markov:
The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings
ACM 2004 |
16 | EE | Louis Scheffer:
Physical CAD changes to incorporate design for lithography and manufacturability.
ASP-DAC 2004: 768-773 |
15 | EE | Richard Goldman,
Kurt Keutzer,
Clive Bittlestone,
Ahsan Bootehsaz,
Shekhar Y. Borkar,
E. Chen,
Louis Scheffer,
Chandramouli Visweswariah:
Is statistical timing statistically significant?
DAC 2004: 498 |
14 | EE | Desmond Kirkpatrick,
Peter J. Osler,
Louis Scheffer,
Prashant Saxena,
Dennis Sylvester:
The great interconnect buffering debate: are you a chicken or an ostrich?
ISPD 2004: 61 |
2003 |
13 | | Dennis Sylvester,
Dirk Stroobandt,
Louis Scheffer,
Payman Zarkesh-Ha:
The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings
ACM 2003 |
12 | EE | Andrew B. Kahng,
Shekhar Borkar,
John M. Cohn,
Antun Domic,
Patrick Groeneveld,
Louis Scheffer,
Jean-Pierre Schoellkopf:
Nanometer design: place your bets.
DAC 2003: 546-547 |
11 | EE | Louis Scheffer:
Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips.
PATMOS 2003: 194 |
10 | EE | Louis Scheffer:
Some conditions under which hierarchical verification is O(N).
IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 643-646 (2003) |
2002 |
9 | EE | Louis Scheffer:
Methodologies and Tools for Pipelined On-Chip Interconnect.
ICCD 2002: 152-157 |
8 | EE | Louis Scheffer:
Explicit computation of performance as a function of process variation.
Timing Issues in the Specification and Synthesis of Digital Systems 2002: 1-8 |
2001 |
7 | EE | Andrew B. Kahng,
Bing J. Sheu,
Nancy Nettleton,
John M. Cohn,
Shekhar Borkar,
Louis Scheffer,
Ed Cheng,
Sang Wang:
Panel: Is Nanometer Design Under Control?
DAC 2001: 591-592 |
6 | EE | Hsiao-Ping Tseng,
Louis Scheffer,
Carl Sechen:
Timing- and crosstalk-driven area routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 528-544 (2001) |
2000 |
5 | EE | Raul Camposano,
Jacob Greidinger,
Patrick Groeneveld,
Michael Jackson,
Lawrence T. Pileggi,
Louis Scheffer:
Design closure (panel session): hope or hype?
DAC 2000: 176-177 |
4 | EE | Louis Scheffer,
Eric Nequist:
Why interconnect prediction doesn't work.
SLIP 2000: 139-144 |
1998 |
3 | EE | Hsiao-Ping Tseng,
Louis Scheffer,
Carl Sechen:
Timing and Crosstalk Driven Area Routing.
DAC 1998: 378-381 |
1997 |
2 | EE | Louis Scheffer:
A roadmap of CAD tool changes for sub-micron interconnect problems.
ISPD 1997: 104-109 |
1985 |
1 | EE | Louis Scheffer,
Ronny Soetarman:
Hierarchical analysis of IC artwork with user defined abstraction rules.
DAC 1985: 293-298 |