dblp.uni-trier.dewww.uni-trier.de

Bart Durinck

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2008
6EEIlya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt: Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1439-1452 (2008)
2007
5EEMinas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck CoRR abs/0710.4656: (2007)
2006
4EEIlya Issenin, Erik Brockmeyer, Bart Durinck, Nikil Dutt: Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies. DAC 2006: 49-52
3EEMinas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis: A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck. IEEE Trans. VLSI Syst. 14(3): 279-291 (2006)
2005
2EEMinas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck. DATE 2005: 946-947
2004
1EEMinas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications. SAMOS 2004: 540-549

Coauthor Index

1Erik Brockmeyer [1] [2] [3] [4] [5] [6]
2Francky Catthoor [1] [2] [3] [5]
3Minas Dasygenis [1] [2] [3] [5]
4Nikil D. Dutt (Nikil Dutt) [4] [6]
5Ilya Issenin [4] [6]
6Dimitrios Soudris (D. J. Soudris) [1] [2] [3] [5]
7Adonios Thanailakis (Antonios Thanailakis) [1] [2] [3] [5]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)