2009 |
3 | EE | Mei-Fang Chiang,
Takumi Okamoto,
Takeshi Yoshimura:
Lagrangian relaxation based register placement for high-performance circuits.
ISQED 2009: 511-516 |
2008 |
2 | EE | Huang-Yu Chen,
Mei-Fang Chiang,
Yao-Wen Chang,
Lumdo Chen,
Brian Han:
Full-Chip Routing Considering Double-Via Insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 844-857 (2008) |
2006 |
1 | EE | Huang-Yu Chen,
Mei-Fang Chiang,
Yao-Wen Chang,
Lumdo Chen,
Brian Han:
Novel full-chip gridless routing considering double-via insertion.
DAC 2006: 755-760 |