| 2008 |
|---|
| 6 | EE | Stephan Eggersglüß,
Rolf Drechsler:
On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults.
ISMVL 2008: 94-99 |
| 5 | EE | Rolf Drechsler,
Stephan Eggersglüß,
Görschwin Fey,
Andreas Glowatz,
Friedrich Hapke,
Jürgen Schlöffel,
Daniel Tille:
On Acceleration of SAT-Based ATPG for Industrial Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1329-1333 (2008) |
| 2007 |
|---|
| 4 | EE | Stephan Eggersglüß,
Görschwin Fey,
Rolf Drechsler:
SAT-based ATPG for Path Delay Faults in Sequential Circuits.
ISCAS 2007: 3671-3674 |
| 3 | EE | Stephan Eggersglüß,
Daniel Tille,
Görschwin Fey,
Rolf Drechsler,
Andreas Glowatz,
Friedrich Hapke,
Jürgen Schlöffel:
Experimental Studies on SAT-Based ATPG for Gate Delay Faults.
ISMVL 2007: 6 |
| 2 | EE | Stephan Eggersglüß,
Görschwin Fey,
Rolf Drechsler,
Andreas Glowatz,
Friedrich Hapke,
Jürgen Schlöffel:
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults.
MEMOCODE 2007: 181-187 |
| 1 | EE | Robert Wille,
Görschwin Fey,
Daniel Große,
Stephan Eggersglüß,
Rolf Drechsler:
SWORD: A SAT like prover using word level information.
VLSI-SoC 2007: 88-93 |
