Jens Sparsø

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17EEMikkel Bystrup Stensgaard, Jens Sparsø: ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology. NOCS 2008: 55-64
16EEShankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen: A Reactive and Cycle-True IP Emulator for MPSoC Exploration. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 109-122 (2008)
15EETobias Bjerregaard, Mikkel Bystrup Stensgaard, Jens Sparsø: A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method. DATE 2007: 648-653
14EEMikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Sparsø, Johnny Halkjær Pedersen: A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip. DSD 2006: 641-648
13EETobias Bjerregaard, Jens Sparsø: Packetizing OCP Transactions in the MANGO Network-on-Chip. DSD 2006: 657-664
12EETobias Bjerregaard, Jens Sparsø: A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip. ASYNC 2005: 34-43
11EETobias Bjerregaard, Jens Sparsø: A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip. DATE 2005: 1226-1231
10EEShankar Mahadevan, Federico Angiolini, Michael Storgaard, Rasmus Grøndahl Olsen, Jens Sparsø, Jan Madsen: A Network Traffic Generator Model for Fast Network-on-Chip Simulation. DATE 2005: 780-785
9EEShankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen: A Traffic Injection Methodology with Support for System-Level Synchronization. VLSI-SoC 2005: 145-161
8EES. F. Nielsen, Jens Sparsø, Jan Madsen: Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation. DSD 2004: 298-305
7EETobias Bjerregaard, Shankar Mahadevan, Jens Sparsø: A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling. PATMOS 2004: 301-310
6EEÖzgün Paker, Jens Sparsø, Niels Haandbæk, Mogens Isager, Lars Skovby Nielsen: A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing. VLSI Signal Processing 37(1): 95-110 (2004)
5EEVojin G. Oklobdzija, Jens Sparsø: Future directions in clocking multi-ghz systems. ISLPED 2002: 219
4EEKåre T. Christensen, Peter Jensen, Peter Korger, Jens Sparsø: The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core. ASYNC 1998: 108-
3EELars Skovby Nielsen, C. Niessen, Jens Sparsø, Kees van Berkel: Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. IEEE Trans. VLSI Syst. 2(4): 391-397 (1994)
2 Jens Sparsø, Christian D. Nielsen, Lars Skovby Nielsen, Jørgen Staunstrup: Design of Self-timed Multipliers: A Comparison. Asynchronous Design Methodologies 1993: 165-179
1 Jens Sparsø, Steen Pedersen, Erik Paaske: Design of a Fully Parallel Viterbi Decoder. VLSI 1991: 29-38

Coauthor Index

1Federico Angiolini [9] [10] [16]
2Luca Benini [9] [16]
3Kees van Berkel [3]
4Tobias Bjerregaard [7] [11] [12] [13] [14] [15]
5Kåre T. Christensen [4]
6Niels Haandbæk [6]
7Mogens Isager [6]
8Peter Jensen [4]
9Peter Korger [4]
10Jan Madsen [8] [9] [10] [16]
11Shankar Mahadevan [7] [9] [10] [16]
12Christian D. Nielsen [2]
13Lars Skovby Nielsen [2] [3] [6]
14S. F. Nielsen [8]
15C. Niessen [3]
16Vojin G. Oklobdzija [5]
17Rasmus Grøndahl Olsen [10]
18Erik Paaske [1]
19Özgün Paker [6]
20Johnny Halkjær Pedersen [14]
21Steen Pedersen [1]
22Jørgen Staunstrup [2]
23Mikkel Bystrup Stensgaard [14] [15] [17]
24Michael Storgaard [10]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)