| 2008 |
|---|
| 4 | EE | Hsin-Chen Chen,
Yi-Lin Chuang,
Yao-Wen Chang,
Yung-Chung Chang:
Constraint graph-based macro placement for modern mixed-size circuit designs.
ICCAD 2008: 218-223 |
| 3 | EE | Tung-Chieh Chen,
Zhe-Wei Jiang,
Tien-Chang Hsu,
Hsin-Chen Chen,
Yao-Wen Chang:
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1228-1240 (2008) |
| 2006 |
|---|
| 2 | EE | Tung-Chieh Chen,
Zhe-Wei Jiang,
Tien-Chang Hsu,
Hsin-Chen Chen,
Yao-Wen Chang:
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints.
ICCAD 2006: 187-192 |
| 1 | EE | Zhe-Wei Jiang,
Tung-Chieh Chen,
Tien-Chang Hsu,
Hsin-Chen Chen,
Yao-Wen Chang:
NTUplace2: a hybrid placer using partitioning and analytical techniques.
ISPD 2006: 215-217 |
