| |
| 2008 | ||
|---|---|---|
| 5 | EE | Khaled R. Heloue, Farid N. Najm: Parameterized timing analysis with general delay models and arbitrary variation sources. DAC 2008: 403-408 |
| 4 | EE | Khaled R. Heloue, Sari Onaissi, Farid N. Najm: Efficient block-based parameterized timing analysis covering all potentially critical paths. ICCAD 2008: 173-180 |
| 3 | EE | Khaled R. Heloue, Farid N. Najm: Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1826-1839 (2008) |
| 2007 | ||
| 2 | EE | Khaled R. Heloue, Navid Azizi, Farid N. Najm: Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation. DAC 2007: 93-98 |
| 2005 | ||
| 1 | Khaled R. Heloue, Farid N. Najm: Statistical timing analysis with two-sided constraints. ICCAD 2005: 829-836 | |
| 1 | Navid Azizi | [2] |
| 2 | Farid N. Najm | [1] [2] [3] [4] [5] |
| 3 | Sari Onaissi | [4] |