| 2008 |
| 15 | EE | Seda Ogrenci Memik,
Nikolaos Bellas,
Somsubhra Mondal:
Presynthesis Area Estimation of Reconfigurable Streaming Accelerators.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2027-2038 (2008) |
| 2007 |
| 14 | EE | Nikolaos Bellas,
Sek M. Chai,
Malcolm Dwyer,
Dan Linzmeier:
An Architectural Framework for Automated Streaming Kernel Selection.
IPDPS 2007: 1-7 |
| 2006 |
| 13 | EE | Somsubhra Mondal,
Seda Ogrenci Memik,
Nikolaos Bellas:
Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs.
FCCM 2006: 325-326 |
| 12 | EE | Nikolaos Bellas,
Sek M. Chai,
Malcolm Dwyer,
Dan Linzmeier:
Template-Based Generation of Streaming Accelators from a High Level Presentation.
FCCM 2006: 345-346 |
| 11 | EE | Somsubhra Mondal,
Seda Ogrenci Memik,
Nikolaos Bellas:
Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators.
FPL 2006: 1-4 |
| 10 | EE | Nikolaos Bellas,
Arnold Yanof:
An Image Processing Pipeline with Digital Compensation of Low Cost Optics for Mobile Telephony.
ICME 2006: 1249-1252 |
| 9 | EE | Nikolaos Bellas,
Sek M. Chai,
Malcolm Dwyer,
Dan Linzmeier:
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators.
IPDPS 2006 |
| 2005 |
| 8 | EE | Georgios I. Stamoulis,
Maria G. Koziri,
Ioannis Katsavounidis,
Nikolaos Bellas:
A Low - Power VLSI Architecture for Intra Prediction in H.264.
Panhellenic Conference on Informatics 2005: 633-640 |
| 2000 |
| 7 | EE | Nikolaos Bellas,
Ibrahim N. Hajj,
Constantine D. Polychronopoulos,
G. Stamoulis:
Architectural and compiler techniques for energy reduction in high-performance microprocessors.
IEEE Trans. VLSI Syst. 8(3): 317-326 (2000) |
| 6 | EE | Nikolaos Bellas,
Ibrahim N. Hajj,
Constantine D. Polychronopoulos:
Using dynamic cache management techniques to reduce energy in general purpose processors.
IEEE Trans. VLSI Syst. 8(6): 693-708 (2000) |
| 1999 |
| 5 | EE | Nikolaos Bellas,
Ibrahim N. Hajj,
Constantine D. Polychronopoulos,
George D. Stamoulis:
Energy and Performance Improvements in Microprocessor Design Using a Loop Cache.
ICCD 1999: 378-383 |
| 4 | EE | Nikolaos Bellas,
Ibrahim N. Hajj,
Constantine D. Polychronopoulos:
An analytical, transistor-level energy model for SRAM-based caches.
ISCAS (6) 1999: 198-201 |
| 3 | EE | Nikolaos Bellas,
Ibrahim N. Hajj,
Constantine D. Polychronopoulos:
Using dynamic cache management techniques to reduce energy in a high-performance processor.
ISLPED 1999: 64-69 |
| 1998 |
| 2 | EE | Nikolaos Bellas,
Ibrahim N. Hajj,
George D. Stamoulis,
Nikolaos Bellas,
Constantine D. Polychronopoulos:
Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors.
ISLPED 1998: 70-75 |
| 1 | EE | Nikolaos Bellas,
Ibrahim N. Hajj,
George D. Stamoulis,
Nikolaos Bellas,
Constantine D. Polychronopoulos:
Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors.
ISLPED 1998: 70-75 |