| 2009 |
|---|
| 21 | EE | Soumya Pandit,
Chittaranjan A. Mandal,
Amit Patra:
Systematic Methodology for High-Level Performance Modeling of Analog Systems.
VLSI Design 2009: 361-366 |
| 2008 |
|---|
| 20 | EE | Chandan Karfa,
Dipankar Sarkar,
Chitta Mandal,
P. Kumar:
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 556-569 (2008) |
| 19 | EE | Soumya Pandit,
Sumit K. Bhattacharya,
Chittaranjan A. Mandal,
Amit Patra:
A Fast Exploration Procedure for Analog High-Level Specification Translation.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1493-1497 (2008) |
| 2007 |
|---|
| 18 | EE | Chandan Karfa,
Dipankar Sarkar,
Chittaranjan A. Mandal,
Chris Reade:
Hand-in-hand verification of high-level synthesis.
ACM Great Lakes Symposium on VLSI 2007: 429-434 |
| 17 | EE | Rajiv Misra,
Chittaranjan A. Mandal:
ClusterHead Rotation via Domatic Partition in Self-Organizing Sensor Networks.
COMSWARE 2007 |
| 16 | EE | Chandan Karfa,
Chittaranjan A. Mandal,
Dipankar Sarkar,
Chris Reade:
Register Sharing Verification During Data-Path Synthesis.
ICCTA 2007: 135-140 |
| 15 | EE | Vinay Vishwakarma,
Chittaranjan A. Mandal,
Shamik Sural:
Automatic Detection of Human Fall in Video.
PReMI 2007: 616-623 |
| 2006 |
|---|
| 14 | EE | Soumya Pandit,
Chittaranjan A. Mandal,
Amit Patra:
A formal approach for high level synthesis of linear analog systems.
ACM Great Lakes Symposium on VLSI 2006: 345-348 |
| 13 | EE | Soumya Pandit,
Sougata Kar,
Chittaranjan A. Mandal,
Amit Patra:
High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count.
DATE 2006: 1203-1204 |
| 12 | EE | Chandan Karfa,
Chittaranjan A. Mandal,
Dipankar Sarkar,
S. R. Pentakota,
Chris Reade:
A Formal Verification Method of Scheduling in High-level Synthesis.
ISQED 2006: 71-78 |
| 11 | EE | Chandan Karfa,
Chittaranjan A. Mandal,
Dipankar Sarkar,
S. R. Pentakota,
Chris Reade:
Verification of Scheduling in High-level Synthesis.
ISVLSI 2006: 141-146 |
| 10 | | Amit Kumar Mandal,
Chittaranjan A. Mandal,
Chris Reade:
A System for Automatic Evaluation of Programs for Correctness and Performance.
WEBIST (2) 2006: 196-203 |
| 9 | | Chittaranjan A. Mandal,
Chris Reade:
Animating Algorithms over the Web.
WEBIST (2) 2006: 403-407 |
| 8 | EE | Amit Kumar Mandal,
Chittaranjan A. Mandal,
Chris Reade:
A System for Automatic Evaluation of Programs for Correctness and Performance.
WEBIST (Selected Papers) 2006: 367-380 |
| 2004 |
|---|
| 7 | EE | Arijit Mondal,
P. P. Chakrabarti,
Chittaranjan A. Mandal:
A New Approach to Timing Analysis Using Event Propagation and Temporal Logic.
DATE 2004: 1198-1203 |
| 2002 |
|---|
| 6 | EE | B. Rajendran,
V. Kheterpal,
A. Das,
J. Majumder,
Chittaranjan A. Mandal,
P. P. Chakrabarti:
Timing analysis of tree-like RLC circuits.
ISCAS (4) 2002: 838-841 |
| 2000 |
|---|
| 5 | EE | Chittaranjan A. Mandal,
R. M. Zimmer:
A Genetic Algorithm for the Synthesis of Structured Data Paths.
VLSI Design 2000: 206-211 |
| 4 | EE | Chittaranjan A. Mandal,
P. P. Chakrabarti,
Sujoy Ghose:
GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths.
IEEE Trans. VLSI Syst. 8(6): 747-750 (2000) |
| 1999 |
|---|
| 3 | EE | Chittaranjan A. Mandal,
P. P. Chakrabarti,
Sujoy Ghose:
A design space exploration scheme for data-path synthesis.
IEEE Trans. VLSI Syst. 7(3): 331-338 (1999) |
| 1997 |
|---|
| 2 | EE | Chittaranjan A. Mandal,
P. P. Chakrabarti,
Sujoy Ghose:
Design Space Exploration for Data Path Synthesis.
VLSI Design 1997: 166-173 |
| 1996 |
|---|
| 1 | EE | Chittaranjan A. Mandal,
P. P. Chakrabarti,
Sujoy Ghose:
Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach.
VLSI Design 1996: 122-125 |
