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Mark Kassab

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2008
13EEJanusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Neelanjan Mukherjee, Mark Kassab: X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 147-159 (2008)
2007
12EEDhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski: Test Generation in the Presence of Timing Exceptions and Constraints. DAC 2007: 688-693
11EEJerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai: X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Design & Test of Computers 24(5): 476-485 (2007)
2004
10EEBrady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski: Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. ITC 2004: 1285-1294
9EEXinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski: Realizing High Test Quality Goals with Smart Test Resource Usage. ITC 2004: 525-533
8EEJanusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee: Embedded deterministic test. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 776-792 (2004)
2003
7EEFrank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski: Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. ITC 2003: 1211-1220
6EEJanusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian: Embedded Deterministic Test for Low-Cost Manufacturing. IEEE Design & Test of Computers 20(5): 58-66 (2003)
2002
5EEJanusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian: Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC 2002: 301-310
1999
4 Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski: Logic BIST for large industrial designs: real issues and case studies. ITC 1999: 358-367
1998
3EEAiman H. El-Maleh, Mark Kassab, Janusz Rajski: A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. DAC 1998: 625-631
1995
2EEMark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Software Accelerated Functional Fault Simulation for Data-Path Architectures. DAC 1995: 333-338
1 Mark Kassab, Janusz Rajski, Jerzy Tyszer: Hierarchical Functional-Fault Simulation for High-Level Synthesis. ITC 1995: 596-605

Coauthor Index

1Ralf Arnold [7]
2Matthias Beck [7]
3Brady Benware [10]
4Wu-Tung Cheng [11] [13]
5Geir Eide [5]
6Bill Eklow (William Eklow) [9]
7Aiman H. El-Maleh (Aiman El-Maleh) [3]
8Tony Fryars [4]
9Dhiraj Goswami [12]
10Xinli Gu [9]
11Abu S. M. Hassan [4]
12Andre Hertwig [5]
13Graham Hetherington [4]
14Martin Keim [10]
15Prabhu Krishnamurthy [10]
16Liyang Lai [11]
17Abby Lee [9]
18Cam Lu [10]
19Robert Madge [10]
20Grzegorz Mrugalski [5] [11] [13]
21Peter Muhmenthaler [7]
22Neelanjan Mukherjee [13]
23Nilanjan Mukherjee [2] [5] [6] [7] [8] [11]
24Frank Poehl [7]
25Jun Qian [5] [6]
26Janusz Rajski [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
27Manish Sharma [11]
28John Van Slyke [10]
29Nagesh Tamarapalli [4] [5] [6] [7]
30Rob Thompson [5]
31Jan Arild Tofte [9]
32Kun-Han Tsai [5] [9] [12]
33Jerzy Tyszer [1] [2] [5] [6] [8] [11] [13]
34Cyndee Wang [9]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)