2008 | ||
---|---|---|
36 | EE | Ruchir Puri, Devadas Varma, Darvin Edwards, Alan J. Weger, Paul Franzon, Andrew Yang, Stephen V. Kosonocky: Keeping hot chips cool: are IC thermal problems hot air? DAC 2008: 634-635 |
35 | EE | Ruchir Puri, William H. Joyner, Shekhar Borkar, Ty Garibay, Jonathan Lotz, Robert K. Montoye: Custom is from Venus and synthesis from Mars. DAC 2008: 992 |
34 | EE | Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong: Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 621-632 (2008) |
33 | EE | Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong: Fast Dummy-Fill Density Analysis With Coupling Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 633-642 (2008) |
32 | EE | Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan: Track Routing and Optimization for Yield. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 872-882 (2008) |
2007 | ||
31 | EE | Srikanth Venkataraman, Ruchir Puri, Steve Griffith, Ankush Oberai, Robert Madge, Greg Yeric, Walter Ng, Yervant Zorian: Making Manufacturing Work For You. DAC 2007: 107-108 |
30 | EE | Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan: TROY: Track Router with Yield-driven Wire Planning. DAC 2007: 55-58 |
29 | EE | Kerry Bernstein, Paul Andry, Jerome Cann, Philip G. Emma, David Greenberg, Wilfried Haensch, Mike Ignatowski, Steve Koester, John Magerlein, Ruchir Puri, Albert M. Young: Interconnects in the Third Dimension: Design Challenges for 3D ICs. DAC 2007: 562-567 |
28 | EE | Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong: Is your layout density verification exact?: a fast exact algorithm for density calculation. ISPD 2007: 19-26 |
27 | EE | Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong: Dummy fill density analysis with coupling constraints. ISPD 2007: 3-10 |
2006 | ||
26 | EE | Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky: Gain-based technology mapping for minimum runtime leakage under input vector uncertainty. DAC 2006: 522-527 |
25 | EE | David J. Frank, Ruchir Puri, Dorel Toma: Design and CAD challenges in 45nm CMOS and beyond. ICCAD 2006: 329-333 |
24 | EE | Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri: Wire density driven global routing for CMP variation and timing. ICCAD 2006: 487-492 |
23 | EE | Ruchir Puri, Tanay Karnik, Rajiv V. Joshi: Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. VLSI Design 2006: 5-7 |
2005 | ||
22 | EE | Ruchir Puri, Leon Stok, Subhrajit Bhattacharya: Keeping hot chips cool. DAC 2005: 285-288 |
21 | EE | Ruchir Puri, David S. Kung, Leon Stok: Minimizing power with flexible voltage islands. ISCAS (1) 2005: 21-24 |
20 | EE | Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi: Design of sub-90nm Circuits and Design Methodologies. ISQED 2005: 3-4 |
2004 | ||
19 | EE | Louise Trevillyan, David S. Kung, Ruchir Puri, Lakshmi N. Reddy, Michael A. Kazda: An Integrated Environment for Technology Closure of Deep-Submicron IC Designs. IEEE Design & Test of Computers 21(1): 14-22 (2004) |
2003 | ||
18 | EE | Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni: Pushing ASIC performance in a power envelope. DAC 2003: 788-793 |
17 | EE | Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri: Design and CAD Challenges in sub-90nm CMOS Technologies. ICCAD 2003: 129-137 |
16 | EE | Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim: Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. ISQED 2003: 153-158 |
2002 | ||
15 | EE | Ruchir Puri, David S. Kung, Anthony D. Drumm: Fast and accurate wire delay estimation for physical synthesis of large ASICs. ACM Great Lakes Symposium on VLSI 2002: 30-36 |
2000 | ||
14 | EE | Ruchir Puri, Ching-Te Chuang: SOI Digital Circuits: Design Issues. VLSI Design 2000: 474-479 |
13 | EE | Frederik Beeftink, Prabhakar Kudva, David S. Kung, Ruchir Puri, Leon Stok: Combinatorial cell design for CMOS libraries. Integration 29(1): 67-93 (2000) |
1999 | ||
12 | EE | Ching-Te Chuang, Ruchir Puri: SOI Digital CMOS VLSI - a Design Perspective. DAC 1999: 709-714 |
11 | EE | David S. Kung, Ruchir Puri: Optimal P/N width ratio selection for standard cell libraries. ICCAD 1999: 178-184 |
10 | EE | Ruchir Puri, Ching-Te Chuang: Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits. ISLPED 1999: 223-228 |
1996 | ||
9 | EE | Ruchir Puri, Andrew Bjorksten, Thomas E. Rosser: Logic optimization by output phase assignment in dynamic logic synthesis. ICCAD 1996: 2-7 |
8 | Ruchir Puri, Jun Gu: A BDD SAT Solver for Satisfiability Testing: An Industrial Case Study. Ann. Math. Artif. Intell. 17(3-4): 315-337 (1996) | |
1995 | ||
7 | EE | Jun Gu, Ruchir Puri: Asynchronous circuit synthesis with Boolean satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 961-973 (1995) |
1994 | ||
6 | EE | Ruchir Puri, Jun Gu: A Modular Partitioning Approach for Asynchronous Circuit Synthesis. DAC 1994: 63-69 |
5 | Ruchir Puri, Jun Gu: Area Efficient Synthesis of Asynchronous Interface Circuits. ICCD 1994: 212-216 | |
1993 | ||
4 | Ruchir Puri, Jun Gu: Signal Transition Graph Constraints for Speed-independent Ciruit Synthesis. ISCAS 1993: 1686-1689 | |
3 | EE | Ruchir Puri, Jun Gu: Microword length minimization in microprogrammed controller synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1449-1457 (1993) |
2 | EE | Ruchir Puri, Jun Gu: An efficient algorithm to search for minimal closed covers in sequential machines. IEEE Trans. on CAD of Integrated Circuits and Systems 12(6): 737-745 (1993) |
1992 | ||
1 | EE | Ruchir Puri, Jun Gu: An Efficient algorithm for Microword Length Minimization. DAC 1992: 651-656 |