2008 | ||
---|---|---|
73 | EE | Ji-Hoon Kim, In-Cheol Park: Duo-binary circular turbo decoder based on border metric encoding for WiMAX. ASP-DAC 2008: 109-110 |
72 | EE | Tae-Hwan Kim, In-Cheol Park: Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems. ASP-DAC 2008: 111-112 |
71 | EE | Jeong-Ho Han, In-Cheol Park: Digital filter synthesis considering multiple adder graphs for a coefficient. ICCD 2008: 315-320 |
70 | EE | Jeong-Sup Lee, In-Cheol Park: Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters. ISCAS 2008: 236-239 |
69 | EE | Hae-Soo Jeon, Duk-Hyun You, In-Cheol Park: Fast frequency acquisition all-digital PLL using PVT calibration. ISCAS 2008: 2625-2628 |
68 | EE | WonHee Son, In-Cheol Park: Prediction-based real-time CABAC decoder for high definition H.264/AVC. ISCAS 2008: 33-36 |
67 | EE | Tae-Hwan Kim, In-Cheol Park: Time-Domain Joint Estimation of Fine Symbol Timing Offset and Integer Carrier Frequency Offset. VTC Spring 2008: 1186-1190 |
66 | EE | Tae-Hwan Kim, In-Cheol Park: Low-Power and High-Accurate Synchronization for IEEE 802.16d Systems. IEEE Trans. VLSI Syst. 16(12): 1620-1630 (2008) |
65 | EE | Jeong-Ho Han, In-Cheol Park: FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 958-962 (2008) |
2007 | ||
64 | EE | In-Cheol Park, WonHee Son, Ji-Hoon Kim: Twiddle factor transformation for pipelined FFT processing. ICCD 2007: 1-6 |
63 | EE | Ji-Hoon Kim, In-Cheol Park: Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding. ISCAS 2007: 1325-1328 |
62 | EE | Jung-Wook Kim, Jinook Song, Seokho Lee, In-Cheol Park: Tiled Interleaving for Multi-Level 2-D Discrete Wavelet Transform. ISCAS 2007: 3984-3987 |
61 | EE | Se-Hyeon Kang, In-Cheol Park: High Speed Sphere Decoding Based on Vertically Incremental Computation. ISCAS 2007: 665-668 |
60 | EE | Se-Hyeon Kang, In-Cheol Park: Fast and Area-Efficient Sphere Decoding Using Look-Ahead Search. VTC Spring 2007: 2384-2388 |
59 | EE | Myoung-Cheol Shin, In-Cheol Park: SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards. IEEE Trans. VLSI Syst. 15(7): 801-810 (2007) |
58 | EE | Ji-Hoon Kim, In-Cheol Park: Long-Point FFT Processing Based on Twiddle Factor Table Reduction. IEICE Transactions 90-A(11): 2526-2532 (2007) |
57 | EE | Chung-Hyo Kim, In-Cheol Park: Parallel Decoding of Context-Based Adaptive Binary Arithmetic Codes Based on Most Probable Symbol Prediction. IEICE Transactions 90-D(2): 609-612 (2007) |
2006 | ||
56 | EE | Kimo Kim, In-Cheol Park: Combined image signal processing for CMOS image sensors. ISCAS 2006 |
55 | EE | Chung-Hyo Kim, In-Cheol Park: High speed decoding of context-based adaptive binary arithmetic codes using most probable symbol prediction. ISCAS 2006 |
54 | EE | Hye-Mi Choi, Ji-Hoon Kim, In-Cheol Park: Low-power hybrid turbo decoding based on reverse calculation. ISCAS 2006 |
53 | EE | Hye-Mi Choi, Ji-Hoon Kim, In-Cheol Park: Low-Power Hybrid Turbo Decoding Based on Reverse Calculation. IEICE Transactions 89-A(3): 782-789 (2006) |
2005 | ||
52 | EE | Dong-Soo Lee, In-Cheol Park: Low-power log-MAP turbo decoding based on reduced metric memory access. ISCAS (4) 2005: 3167-3170 |
51 | EE | In-Cheol Park, Se-Hyeon Kang: Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation. ISCAS (6) 2005: 5778-5781 |
50 | EE | Hyeong-Ju Kang, In-Cheol Park: SAT-based unbounded symbolic model checking. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 129-140 (2005) |
49 | EE | Dong-Soo Lee, In-Cheol Park: A Low-Complexity Stopping Criterion for Iterative Turbo Decoding. IEICE Transactions 88-B(1): 399-401 (2005) |
48 | EE | Jong-Yeol Lee, Seong Ik Cho, In-Cheol Park: Performance enhancement of embedded software based on new register allocation technique. Microprocessors and Microsystems 29(4): 177-187 (2005) |
2004 | ||
47 | Hyun-Yong Lee, In-Cheol Park: A fast Reed-Solomon Product-Code decoder without redundant computations. ISCAS (2) 2004: 381-384 | |
46 | Se-Hyeon Kang, In-Cheol Park: Memory-based low density parity check code decoder architecture using loosely coupled two data-flows. ISCAS (2) 2004: 397-400 | |
45 | Sung-Won Lee, In-Cheol Park: Quadrature direct digital frequency synthesis using fine-grain angle rotation. ISCAS (2) 2004: 709-712 | |
2003 | ||
44 | EE | Hyeong-Ju Kang, In-Cheol Park: SAT-based unbounded symbolic model checking. DAC 2003: 840-843 |
43 | EE | In-Cheol Park, Se-Hyeon Kang, Yongseok Yi: Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation. ICCAD 2003: 138-141 |
42 | EE | Jae Hoon Shim, In-Cheol Park, Beomsup Kim: A hybrid delta-sigma modulator with adaptive calibration. ISCAS (1) 2003: 1025-1028 |
41 | EE | Hyung Ki Ahn, In-Cheol Park, Beomsup Kim: A 5-GHz self-calibrated I/Q clock generator using a quadrature LC-VCO. ISCAS (1) 2003: 797-800 |
40 | EE | Sung-Won Lee, Hyeong-Ju Kang, In-Cheol Park: A 24-bit floating-point audio DSP controller supporting fast exponentiation. ISCAS (2) 2003: 748-751 |
39 | EE | Hyeong-Ju Kang, In-Cheol Park: Pairing and ordering to reduce hardware complexity in cascade form filter design. ISCAS (4) 2003: 265-268 |
38 | EE | Sang-Chul Moon, In-Cheol Park: Area-efficient memory-based architecture for FFT processing. ISCAS (5) 2003: 101-104 |
37 | EE | Seong-Il Park, In-Cheol Park: History-based memory mode prediction for improving memory performance. ISCAS (5) 2003: 185-188 |
36 | EE | Jong-Yeol Lee, In-Cheol Park: Timed compiled-code functional simulation of embedded software for performance analysis of SOC design. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 1-14 (2003) |
2002 | ||
35 | EE | Jong-Yeol Lee, In-Cheol Park: Timed compiled-code simulation of embedded software for performance analysis of SOC design. DAC 2002: 293-298 |
34 | EE | Sung-Won Lee, In-Cheol Park: Low cost floating-point unit design for audio applications. ISCAS (1) 2002: 869-872 |
33 | EE | Myoung-Cheol Shin, Seong-Il Park, Sung-Won Lee, Se-Hyeon Kang, In-Cheol Park: Area-efficient digital baseband module for Bluetooth wireless communications. ISCAS (5) 2002: 729-732 |
32 | EE | In-Cheol Park, Hyeong-Ju Kang: Digital filter synthesis based on an algorithm to generate all minimal signed digit representations. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1525-1529 (2002) |
31 | EE | Seungjong Lee, Ando Ki, In-Cheol Park, Chong-Min Kyung: Interface synthesis between software chip model and target board. Journal of Systems Architecture 48(1-3): 49-57 (2002) |
2001 | ||
30 | EE | Woo-Seung Yang, In-Cheol Park, Chong-Min Kyung: Low-power high-level synthesis using latches. ASP-DAC 2001: 462-466 |
29 | EE | In-Cheol Park, Hyeong-Ju Kang: Digital Filter Synthesis Based on Minimal Signed Digit Representation. DAC 2001: 468-473 |
28 | Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park: An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking. ICCD 2001: 511-512 | |
27 | EE | Hyeong-Ju Kang, In-Cheol Park: Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders. ISCAS (2) 2001: 693-696 |
26 | EE | Sung-Won Lee, In-Cheol Park: A low-power variable length decoder based on successive decoding of shoft codewords. ISCAS (4) 2001: 582-585 |
25 | EE | Jong-Yeol Lee, In-Cheol Park: Global variable localization and transformation for hardware synthesis from high-level programming language description. ISCAS (5) 2001: 13-16 |
24 | Hansoo Kim, In-Cheol Park: High-performance and low-power memory-interface architecture for video processing applications. IEEE Trans. Circuits Syst. Video Techn. 11(11): 1160-1170 (2001) | |
2000 | ||
23 | EE | Young-Su Kwon, In-Cheol Park, Chong-Min Kyung: A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics. ASP-DAC 2000: 559-564 |
22 | Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park: FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders. ICCAD 2000: 51-54 | |
21 | EE | Bong-Il Park, Hoon Choi, In-Cheol Park, Chong-Min Kyung: Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies. ICCD 2000: 519-524 |
20 | Young-Su Kwon, In-Cheol Park, Chong-Min Kyung: Pyramid Texture Compression and Decompression Using Interpolative Vector Quantization. ICIP 2000 | |
19 | Myoung-Cheol Shin, In-Cheol Park: Optimal down-conversion in compressed DCT domain with minimal operations. VCIP 2000: 1613-1620 | |
18 | Hansoo Kim, In-Cheol Park: Array address translation for SDRAM-based video processing applications. VCIP 2000: 922-931 | |
17 | EE | Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Joon Nam, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Chan-Soo Hwang, Yong-Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung: MetaCore: an application-specific programmable DSP development system. IEEE Trans. VLSI Syst. 8(2): 173-183 (2000) |
1999 | ||
16 | EE | Young-Su Kwon, Bong-Il Park, In-Cheol Park, Chong-Min Kyung: A New Single-Clock Flip-Clop for Half-Swing Clocking. ASP-DAC 1999: 117-120 |
15 | EE | Hoon Choi, Hansoo Kim, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung: Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods. ASP-DAC 1999: 157-160 |
14 | EE | You-Sung Chang, Seungjong Lee, In-Cheol Park, Chong-Min Kyung: Verification of a Microprocessor Using Real World Applications. DAC 1999: 181-184 |
13 | EE | Hoon Choi, Ju Hwan Yi, Jong-Yeol Lee, In-Cheol Park, Chong-Min Kyung: Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software. DAC 1999: 939-944 |
12 | EE | You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong-Min Kyung: Customization of a CISC Processor Core for Low-Power Applications. ICCD 1999: 152- |
11 | EE | Bong-Il Park, In-Cheol Park, Chong-Min Kyung: A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders. ICCD 1999: 243- |
10 | Hoon Choi, Jong-Sun Kim, Chi-Won Yoon, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung: Synthesis of Application Specific Instructions for Embedded DSP Software. IEEE Trans. Computers 48(6): 603-614 (1999) | |
1998 | ||
9 | EE | Namseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheol Park, Chong-Min Kyung: Virtual Chip: Making Functional Models Work on Real Target Systems. DAC 1998: 170-173 |
8 | EE | Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Sung-Won Seo, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun Sung Kim, Kwang-Il Park, Kyu Ho Park, Yong-Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung: MetaCore: An Application Specific DSP Development System. DAC 1998: 800-803 |
7 | EE | Ju Hwan Yi, Hoon Choi, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung: Multiple Behavior Module Synthesis Based on Selective Groupings. DATE 1998: 384-388 |
6 | EE | Hoon Choi, Seung Ho Hwang, Chong-Min Kyung, In-Cheol Park: Synthesis of application specific instructions for embedded DSP software. ICCAD 1998: 665-671 |
1997 | ||
5 | EE | Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung: A C-Based RTL Design Verification Methodology for Complex Microprocessor. DAC 1997: 83-88 |
1994 | ||
4 | In-Cheol Park, Se-Kyoung Hong, Chong-Min Kyung: Two Complementary Approaches for Microcode Bit Optimization. IEEE Trans. Computers 43(2): 234-239 (1994) | |
1993 | ||
3 | EE | In-Cheol Park, Chong-Min Kyung: FAMOS: an efficient scheduling algorithm for high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1437-1448 (1993) |
1991 | ||
2 | EE | In-Cheol Park, Chong-Min Kyung: Fast and Near Optimal Scheduling in Automatic Data Path Aynthesis. DAC 1991: 680-685 |
1990 | ||
1 | Se-Kyoung Hong, In-Cheol Park, Chong-Min Kyung: An O(n3logn)-Heuristic for Microcode Bit Optimization. ICCAD 1990: 180-183 |